| _ | vlsi | _ |
|---|
| 124 Mpixels/s | vlsi | Design for Histogram-Based Joint Bilateral Filtering, A |
| 1ms | vlsi | Vision Chip System and Its Applications |
| Algorithm and | vlsi | Architecture Co-Design on Efficient Semi-Global Stereo Matching |
| algorithm and | vlsi | architecture of a high efficient motion estimation with adaptive search range for HEVC systems, The |
| Algorithm and | vlsi | Architecture of Edge-Directed Image Upscaling for 4k Display System |
| Algorithm partition and parallel recognition of general context-free languages using fixed-size | vlsi | architecture |
| Algorithm-based low-power | vlsi | architecture for 2-D mesh video-object motion tracking |
| Algorithms, Complexity Analysis and | vlsi | Architectures for MPEG-4 Motion Estimation |
| Analog | vlsi | Architectures for Motion Processing: From Fundamental Limits to System Applications |
| Analog | vlsi | Circuits for Stimulus Localization and Centroid Computation |
| Analog | vlsi | Neuromorphic Image Acquisition and Preprocessing Systems |
| Analog | vlsi | System for Stereoscopic Vision, An |
| Analog | vlsi | Systems for Image Acquisition and Fast Early Vision Processing |
| Analysis and | vlsi | Implementation of EWA Rendering for Real-Time HD Video Applications |
| Analysis, Fast Algorithm, and | vlsi | Architecture Design for H.264/AVC Intra Frame Coder |
| Architecture for Region Boundary Extraction in Raster Scan Images Suitable for | vlsi | Implementation, An |
| Area Efficient | vlsi | Architecture of a Reed-Solomon Decoder/Encoder for Digital VCRs, An |
| ASIC-architecture for | vlsi | -implementation of the RBN-algorithm, An |
| ATA: Attentional Non-Linear Activation Function Approximation for | vlsi | -Based Neural Networks |
| Attribute Grammar for Shape Recognition and Its | vlsi | Implementation |
| Biologically Inspired Visual Motion Detection in | vlsi | |
| Bit-Serial | vlsi | Architecture for Generating Moments in Real Time, A |
| Boundary correlation-based intracoding for SHVC algorithm and its efficient | vlsi | architecture |
| Buffer structure optimized | vlsi | architecture for efficient hierarchical integer pixel motion estimation implementation |
| CASM: A | vlsi | Chip for Approximate String-Matching |
| Cellular-Automaton for the Determination of the Mean Velocity of Moving-Objects and Its | vlsi | Implementation, A |
| Coding sensitive based approximation algorithm for power efficient VBS-DCT | vlsi | design in HEVC hardwired Intra encoder |
| Color-Edge Detectors for a | vlsi | Convolver |
| Compact | vlsi | System for Bio-Inspired Visual Motion Estimation, A |
| complete system for NN classification based on a | vlsi | array processor, A |
| Computation of Orientational Filters for Real-Time Computer Vision Problems III: Steerable System and | vlsi | Architecture |
| Computing 3-D Motion in Custom Analog and Digital | vlsi | |
| Computing Motion Using Analog | vlsi | Vision Chips: An Experimental Comparison among Different Approaches |
| Cost Effective | vlsi | Architectures for Full Search Block Matching Motion Estimation Algorithm |
| Depth Perception Using Blurring and Its Application in | vlsi | Wafer Probing |
| Depth-Reliability-Based Stereo-Matching Algorithm and Its | vlsi | Architecture Design |
| Design and | vlsi | implementation of QMF banks |
| Design of HDTV subband filterbanks considering | vlsi | implementation constraints |
| Designing high-throughput VLC decoder. I. Concurrent | vlsi | architectures |
| Development of a | vlsi | chip for real time MPEG-2 video decoder |
| Direct Printability Prediction in | vlsi | Using Features from Orthogonal Transforms |
| Dynamic Wires: An Analog | vlsi | Model for Object-Based Processing |
| Effective correlation vector quantisation algorithm and its | vlsi | architecture |
| Effective Search Point Reduction Algorithm and its | vlsi | Design for HDTV H.264/AVC Variable Block Size Motion Estimation |
| Efficient Adaptive Binary Range Coder and Its | vlsi | Architecture, An |
| Efficient Block-Matching Criterion for Motion Estimation and Its | vlsi | Implementation, An |
| Efficient hierarchical chaotic image encryption algorithm and its | vlsi | realisation |
| Efficient K-Means | vlsi | Architecture for Vector Quantization |
| Efficient Lifting Wavelet Transform for Microprocessor and | vlsi | Applications |
| Efficient Line-Based | vlsi | Architecture for 2-D Lifting DWT |
| Efficient Planar Embedding of Trees for | vlsi | Layouts |
| Efficient reference frame compression scheme for video coding systems: algorithm and | vlsi | design |
| efficient | vlsi | architecture and FPGA implementation of the Finite Ridgelet Transform, An |
| efficient | vlsi | architecture for 4X4 intra prediction in the High Efficiency Video Coding (HEVC) standard, An |
| Efficient | vlsi | architecture for bit plane encoder of JPEG 2000 |
| efficient | vlsi | architecture for CBAC of AVS HDTV decoder, An |
| Efficient | vlsi | Architecture for Edge-Oriented Demosaicking |
| Efficient | vlsi | Architecture for Full-Search Block Matching Algorithms, An |
| Efficient | vlsi | Architecture for Separable 2-D Discrete Wavelet Transform, An |
| Efficient | vlsi | Architecture for Template Matching Based on Moment Preserving Pattern Matching, An |
| Efficient | vlsi | Architecture for Transform-Based Intra Prediction in H.264/AVC, An |
| efficient | vlsi | implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters, An |
| efficient | vlsi | processor chip for variable block size integer motion estimation in H.264/AVC, An |
| Embedded Merging Scheme for | vlsi | Implementation of H.264/AVC Motion Estimation Modules, An |
| Enhanced Mesh Connected | vlsi | Architecture for Parallel Image Processing, An |
| Estimating the Focus of Expansion in Analog | vlsi | |
| Fast Algorithm and Its | vlsi | Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding, A |
| Fast Algorithm and | vlsi | Architecture of Rate Distortion Optimization in H.265-HEVC |
| Fast Algorithms and | vlsi | Architecture Design for HEVC Intra-Mode Decision |
| fast and area-efficient | vlsi | architecture for embedded image coding, A |
| fast block-matching algorithm based on adaptive search area and its | vlsi | architecture for H.264/AVC, A |
| Fast Discrete Periodic Radon Transform for prime sized images: Algorithm, architecture, and | vlsi | /FPGA implementation, The |
| fast matching criterion for | vlsi | implementation of block-based motion estimation, A |
| Fast Mode Decision Algorithm and Its | vlsi | Design for H.264/AVC Intra-Prediction, A |
| Fast SAO estimation algorithm and its | vlsi | architecture |
| fast | vlsi | architecture of a hierarchical block matching algorithm for motion estimation, A |
| feasible | vlsi | engine for soft-input-soft-output for joint source channel codes, A |
| Flexible High-Throughput | vlsi | Architecture with 2-D Data-Reuse for Full-Search Motion Estimation, A |
| Flexible | vlsi | Architecture of Motion Estimator for Video Image Compression |
| Fractional Full-Search Motion Estimation | vlsi | Architecture for H.264/AVC |
| Full custom | vlsi | implementation of high-speed 2-D DCT/IDCT chip |
| Generic | vlsi | Architecture for Block Matching Motion Estimation Algorithms |
| Geometrical Shape-Recognition Using a Cellular Automaton Architecture and Its | vlsi | Implementation |
| Group Properties of Cellular Automata and | vlsi | Applications |
| Hardware, | vlsi | Implementations, Embedded Processors, Sensor Processing |
| Hardware-Efficient Multi-Resolution Block Matching Algorithm and its | vlsi | Architecture for High Definition MPEG-Like Video Encoders, A |
| Hardware-Oriented Gold-Washing Adaptive Vector Quantizer and its | vlsi | Architectures for Image Data Compression, A |
| High performance | vlsi | architecture for the trellis coded quantization |
| High performance | vlsi | implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder |
| high-speed pyramid image coding algorithm for a | vlsi | implementation, A |
| High-Throughput and Multi-Parallel | vlsi | Architecture for HEVC Deblocking Filter, A |
| High-Throughput Block-Matching | vlsi | Architecture with Low Memory Bandwidth |
| high-throughput deblocking filter | vlsi | architecture for HEVC, A |
| High-throughput low-cost | vlsi | architecture for AVC/H.264 CAVLC decoding |
| High-Throughput | vlsi | Architecture for Real-Time Full-HD Gradient Guided Image Filter, A |
| High-throughput | vlsi | architectures for the 1-D and 2-D discrete cosine transforms |
| Highly Efficient | vlsi | Architecture for H.264/AVC CAVLC Decoder, A |
| Highly Efficient | vlsi | Architecture for H.264/AVC Level 5.1 CABAC Decoder, A |
| Image Computations on Reconfigurable | vlsi | Arrays |
| Image filtering techniques and | vlsi | architectures for efficient data extraction in shell rendering |
| Inspection -- Chips, Wafers, PCB, PWB, | vlsi | , IC, Disks, etc. |
| Journal of | vlsi | Signal Processing Systems for Signal Image and Video Technology |
| Line Extraction Method for Automated SEM Inspection of | vlsi | Resist, A |
| Lossless Compression of | vlsi | Layout Image Data |
| Low-Hardware-Cost Motion Estimation with Large Search Range for | vlsi | Multimedia Processors |
| Low-Power | vlsi | Architecture for Full-Search Block-Matching Motion Estimation, A |
| Medium Level Scene Representation Using | vlsi | Smart Hexagonal Sensor with multi-resolution Edge Extraction Capability and Scale Space Integration Co-Processor |
| memory aware and multiplierless | vlsi | architecture for the complete Intra Prediction of the HEVC emerging standard, A |
| Memory Efficient | vlsi | Architecture for QCIF to VGA Resolution Conversion |
| Memory-efficient high-speed | vlsi | implementation of multi-level discrete wavelet transform |
| Mixed-Signal | vlsi | Architecture for Real Time Computer Vision |
| Mixed-Signal | vlsi | Neuroprocessor for Image Restoration, A |
| Modular | vlsi | architectures for real-time full-search-based vector quantization |
| Monolithic Hough Transform Processor Based on Restructurable | vlsi | , A |
| Motion Perception Using Analog | vlsi | |
| Multi-Resolution Block Matching Algorithm and Its | vlsi | Architecture for Fast Motion Estimation in an MPEG-2 Video Encoder |
| Multiple target performance evaluation model for HD video encoder | vlsi | architecture design |
| Mumford and Shah Functional: | vlsi | Analysis and Implementation |
| New Cost-Effective | vlsi | Implementation of a 2-D Discrete Cosine Transform and Its Inverse |
| New Domain for Image Analysis: | vlsi | Circuit Testing, with ROMULAD, Specialized in Parallel Image Processing, A |
| New matrix formulation for two-dimensional DCT/IDCT computation and its distributed-memory | vlsi | implementation |
| New Motion Estimation Algorithm Using Adaptively Quantized Low Bit-Resolution Image and Its | vlsi | Architecture for MPEG2 Video Encoding |
| new programmable | vlsi | architecture for histogram and statistics computation in different windows, A |
| New Reference Frame Recompression Algorithm and Its | vlsi | Architecture for UHDTV Video Codec, A |
| New | vlsi | Architecture of a Hierarchical Motion Estimator for Low Bit-rate Video Coding, A |
| Novel Parallel Approach to Character-Recognition and Its | vlsi | Implementation, A |
| Novel | vlsi | Architecture for Multidimensional Discrete Wavelet Transform, A |
| object recognition system using stochastic knowledge source and | vlsi | parallel architecture, An |
| On the data reuse and memory bandwidth analysis for full-search block-matching | vlsi | architecture |
| On-Chip Memory Optimization Scheme for | vlsi | Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform |
| One-Dimensional Analog | vlsi | Implementation for Nonlinear Real-Time Signal Preprocessing, A |
| Parallel bit-level pipelined | vlsi | processing unit for the histogramming operation |
| Parallel image transformation and its | vlsi | implementation |
| Parallel Parsing Algorithms and | vlsi | Implementation for Syntactic Pattern Recognition |
| Parallel regional projection transformation (RPT) and | vlsi | implementation |
| Parallel | vlsi | Architecture for Approximate Computation of Discrete Hadamard Transform |
| Parallel-pipelined architecture for 2-D ICT | vlsi | implementation |
| Partially Pipelined | vlsi | Implementation Of Blowfish Encryption/decryption Algorithm |
| Pipeline and Parallel-Pipeline FFT Processors for | vlsi | Implementations |
| Programmable | vlsi | Retina for Rough Vision, A |
| Real-Time Edge Detector: Algorithm And | vlsi | Architecture, A |
| real-time H.264/AVC | vlsi | encoder architecture, A |
| Real-Time Motion-Feature-Extraction | vlsi | Employing Digital-Pixel-Sensor-Based Parallel Architecture, A |
| real-time | vlsi | -based architecture for multi-motion estimation, A |
| Real-Time Wavelet Vector Quantization Algorithm and Its | vlsi | Architecture, A |
| Reed-Solomon | vlsi | codec for advanced television |
| Register Length Analysis and | vlsi | Optimization of VBS Hadamard Transform in H.264/AVC |
| RPCT Algorithm and its | vlsi | Implementation |
| Scalable | vlsi | architectures for full-search block matching algorithms |
| Shape Recognition Using a Fixed-Size | vlsi | Architecture |
| SIBA: a | vlsi | systolic array chip for image processing |
| Simplified biorthogonal discrete wavelet transform for | vlsi | architecture design |
| Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog | vlsi | |
| SMAC: A | vlsi | Architecture for Scene Matching |
| Space-Time Domain Expansion Approach to | vlsi | and Its Application to Hierarchical Scene Matching |
| Special Issue: | vlsi | and Parallel Computing for Pattern Recognition and Artificial Intelligence |
| Special Issue: | vlsi | for Computer Vision |
| Straight-line detection on a gated-connection | vlsi | network |
| Synchronizing Large | vlsi | Processor Arrays |
| Synthesis of | vlsi | architectures for tree-structured image coding |
| System Analysis of | vlsi | Architecture for Motion-Compensated Temporal Filtering |
| System-level design of specialized | vlsi | hardware for computing relative orientation |
| Texture Recognition Using a Superfast Cellular Neural Network | vlsi | Chip in a Real Experimental Environment |
| Time Multiplexed | vlsi | Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images |
| Toward Color Image Segmentation in Analog | vlsi | : Algorithm and Hardware |
| Tree Matching Algorithm and | vlsi | Architecture for Real Time 2D Object Classification, A |
| Ultra-High-Throughput | vlsi | Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications |
| Variable-Clock-Cycle-Path | vlsi | Design of Binary Arithmetic Decoder for H.265/HEVC, A |
| Very Fast | vlsi | Rangefinder, A |
| vlsi | Algorithms for the Connected Component Problem |
| vlsi | Architecture Design of Guided Filter for 30 Frames/s Full-HD Video |
| vlsi | architecture design of motion vector processor for H.264/AVC |
| vlsi | architecture design of MPEG-4 shape coding |
| vlsi | Architecture Exploration of Guided Image Filtering for 1080P 60Hz Video Processing |
| vlsi | architecture for 4-D depth filtering |
| vlsi | architecture for a flexible block matching processor |
| vlsi | Architecture for a Half-Edge-Based Corner Detector, A |
| vlsi | architecture for block-matching motion estimation algorithm |
| vlsi | Architecture for Computing Scale Space, A |
| vlsi | architecture for difference picture-based dynamic scene analysis, A |
| vlsi | architecture for discrete wavelet transform, A |
| vlsi | architecture for dynamic scene analysis, A |
| vlsi | Architecture for Dynamic Time-Warp Recognition of Handwritten Symbols |
| vlsi | Architecture for Enhanced Approximate Message Passing Algorithm |
| vlsi | architecture for hierarchical scene matching, A |
| vlsi | architecture for parallel concentration-contour approach |
| vlsi | architecture for real time code book generator and encoder of a vector quantizer, A |
| vlsi | Architecture for Real-Time Edge Linking, A |
| vlsi | Architecture for Real-Time HD1080p View Synthesis Engine |
| vlsi | architecture for real-time image and video processing systems |
| vlsi | architecture for video-object segmentation, A |
| vlsi | Architecture of a Highly Efficient Deblocking Filter for HEVC Systems, The |
| vlsi | architecture of HEVC intra prediction for 8K UHDTV applications |
| vlsi | Architectures for Feature Extraction and Pattern Classification |
| vlsi | Architectures for High-Speed Range Estimation |
| vlsi | architectures for string matching and pattern matching |
| vlsi | Architectures for Video Compression: A Survey |
| vlsi | architectures of the 1-D and 2-D discrete wavelet transforms for JPEG 2000 |
| vlsi | array architecture for Hough transform, A |
| vlsi | Array Architecture for Pattern Analysis and Image Processing |
| vlsi | array architecture for realization of DFT, DHT, DCT and DST, A |
| vlsi | Array Processor Accelerator for K-NN Classification, A |
| vlsi | chip set for DPCM coding of HDTV signals, A |
| vlsi | chip set for high-speed lossless data compression, A |
| vlsi | Curve Detector |
| vlsi | Design and Implementation of a Real-Time Image Segmentation Processor |
| vlsi | Design Methodology for Edge-Preserving Image Reconstruction |
| vlsi | Design of a High-Speed and Area-Efficient JPEG2000 Encoder |
| vlsi | Design of a Wavelet Processing Core |
| vlsi | Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications |
| vlsi | Design of Digital Cellular Neural Networks for Image Processing |
| vlsi | for Moment Computation and Its Application to Breast Cancer Detection |
| vlsi | friendly fast CU/PU mode decision for HEVC intra encoding: Leveraging convolution neural network |
| vlsi | hardware accelerator for dynamic time warping, A |
| vlsi | Hardware for Example-Based Learning |
| vlsi | Image-Processing Architecture Dedicated to Real-Time Quality-Control Analysis in an Industrial-Plant, A |
| vlsi | implementation for low-complexity full-search motion estimation |
| vlsi | Implementation of 2-D Discrete Wavelet Transform for Real-Time Video Signal-Processing |
| vlsi | implementation of a foveal polygon segmentation algorithm |
| vlsi | implementation of a high-resolution depth-sensing SoC based on active structured light, The |
| vlsi | implementation of a parallel, self-organizing learning model, A |
| vlsi | Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder |
| vlsi | Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications |
| vlsi | Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications |
| vlsi | Implementation of an Efficient ASIC Architecture for Real-Time Rotation of Digital Images |
| vlsi | implementation of an ultra-low-cost and low-power image compressor for wireless camera networks |
| vlsi | implementation of anisotropic probabilistic neural network for real-time image scaling |
| vlsi | Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images |
| vlsi | Implementation of Fast Connected Component Labeling Using Finite State Machine Based Cell Network |
| vlsi | Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications |
| vlsi | Implementation of High-Performance Error Concealment Processor for TV Broadcasting |
| vlsi | implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding |
| vlsi | implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor |
| vlsi | implementation of real-time image rotation |
| vlsi | implementation of sliding window DFT |
| vlsi | implementation of star detection and centroid calculation algorithms for star tracking applications |
| vlsi | Implementation of Systolic and 3-D Cellular Architectures for Image Processing |
| vlsi | Implementation of the Motion Estimator with 2-Dimensional Data-Reuse |
| vlsi | implementation study of a 10 Mbit/s video decoder, A |
| vlsi | Implementations of Image and Video Multimedia Processing Systems |
| vlsi | Neuroprocessors for Video Motion Detection |
| vlsi | Processor for Image Processing |
| vlsi | Pyramid Chip for Multiresolution Image Analysis, A |
| vlsi | scalable processor array for motion estimation, A |
| vlsi | Smart Sensor for Fast Range Imaging, A |
| vlsi | Solution to the Vertical Segment Visibility Problem, A |
| vlsi | System Architecture for Lossless Image Compression, A |
| vlsi | -Compatible Computer Vision Algorithm for Stereoscopic Depth Analysis in Real-Time, A |
| vlsi | -oriented algorithm and its implementation for AVS chroma interpolation, A |
| wavelet transform-a CMOS | vlsi | ASIC implementation, The |
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