Moon, Y.H.[Yong Ho],
Kim, G.Y.[Gyu Yeong],
Kim, J.H.[Jae Ho],
An Improved Early Detection Algorithm for All-Zero Blocks in H.264
Video Encoding,
CirSysVideo(15), No. 8, August 2005, pp. 1053-1057.
IEEE DOI
0508
BibRef
Earlier: A2, A1, A3:
An early detection of all-zero DCT blocks in H.264,
ICIP04(I: 453-456).
IEEE DOI
0505
BibRef
Moon, Y.H.[Yong Ho],
A New Coeff-Token Decoding Method With Efficient Memory Access in
H.264/AVC Video Coding Standard,
CirSysVideo(17), No. 6, June 2007, pp. 729-736.
IEEE DOI
0706
BibRef
Moon, Y.H.[Yong Ho],
An Advanced Total_Zeros Decoding Method Based on New Memory
Architecture in H.264/AVC CAVLC,
CirSysVideo(18), No. 9, September 2008, pp. 1312-1317.
IEEE DOI
0810
BibRef
Kwak, S.H.[Sang-Hoon],
Kim, J.W.[Jin-Wook],
Har, D.S.[Dong-Soo],
A Novel Hardware Architecture of Intra-Predictor Generator for
H.264/AVC Codec,
IEICE(E91-D), No. 7, July 2008, pp. 2083-2086.
DOI Link
0807
BibRef
Fan, C.P.[Chih-Peng],
Fast 2-Dimensional 8 x 8 Integer Transform Algorithm Design for
H.264/AVC Fidelity Range Extensions,
IEICE(E89-D), No. 12, December 2006, pp. 3006-3011.
DOI Link
0612
BibRef
Khan, N.A.,
Masud, S.,
Ahmad, A.,
A variable block size motion estimation algorithm for real-time H.264
video encoding,
SP:IC(20), No. 4, April 2006, pp. 306-315.
Elsevier DOI
0605
BibRef
Chen, K.H.,
Guo, J.I.,
Wang, J.S.,
A High-Performance Direct 2-D Transform Coding IP Design for MPEG-4
AVC/H.264,
CirSysVideo(16), No. 4, April 2006, pp. 472-483.
IEEE DOI
0605
BibRef
Ku, C.W.,
Cheng, C.C.,
Yu, G.S.,
Tsai, M.C.,
Chang, T.S.,
A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and
Still Camera Applications,
CirSysVideo(16), No. 8, August 2006, pp. 917-928.
IEEE DOI
0609
BibRef
Amer, I.[Ihab],
Badawy, W.[Wael],
Jullien, G.[Graham],
A proposed hardware reference model for spatial transformation and
quantization in H.264,
JVCIR(17), No. 2, April 2006, pp. 533-552.
Elsevier DOI
0711
H.264; Advanced video coding; DCT; Hadamard; Hardware; VLSI;
FPGA; ASIC; Transform; Quantization; Video coding
BibRef
Chen, Y.K.[Yen-Kuang],
Li, E.Q.[Eric Q.],
Zhou, X.S.[Xiao-Song],
Ge, S.[Steven],
Implementation of H.264 encoder and decoder on personal computers,
JVCIR(17), No. 2, April 2006, pp. 509-532.
Elsevier DOI
0711
H.264; Video codec; Multimedia; MMX/SSE Technologies; SIMD;
Hyper-Threading Technology; Multi-threading
BibRef
Ren, J.F.[Jian-Feng],
Kehtarnavaz, N.[Nasser],
Budagavi, M.[Madhukar],
A fast feature-assisted adaptive early termination approach for
multiple reference frames motion estimation in H.264,
RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
Springer DOI
0804
BibRef
Ren, J.F.[Jian-Feng],
Kehtarnavaz, N.[Nasser],
Fast adaptive termination mode selection for H.264 scalable video
coding,
RealTimeIP(4), No. 1, March 2009, pp. xx-yy.
Springer DOI
0903
BibRef
Earlier:
Fast adaptive early termination for mode selection in H.264 scalable
video coding,
ICIP08(2464-2467).
IEEE DOI
0810
BibRef
Babionitakis, K.,
Doumenis, G.,
Georgakarakos, G.,
Lentaris, G.,
Nakos, K.,
Reisis, D.,
Sifnaios, I.,
Vlassopoulos, N.,
A real-time H.264/AVC VLSI encoder architecture,
RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
Springer DOI
0804
BibRef
Po, L.M.,
Guo, K.,
Transform-Domain Fast Sum of the Squared Difference Computation for
H.264/AVC Rate-Distortion Optimization,
CirSysVideo(17), No. 6, June 2007, pp. 765-773.
IEEE DOI
0706
BibRef
Yang, C.L.[Chun-Ling],
Po, L.M.[Lai-Man],
Lam, W.H.[Wing-Hong],
A fast H.264 intra prediction algorithm using macroblock properties,
ICIP04(I: 461-464).
IEEE DOI
0505
BibRef
Jung, B.[Bongsoo],
Jeon, B.W.[Byeung-Woo],
Adaptive slice-level parallelism for H.264/AVC encoding using pre
macroblock mode selection,
JVCIR(19), No. 8, December 2008, pp. 558-572.
Elsevier DOI
0804
Parallelism; Parallel processing; Thread-level parallelism;
Slice-level parallelism; H.264/AVC; Fast inter mode selection; Fast
mode decision; Selective intra coding
BibRef
Yi, Y.,
Song, B.C.,
High-Speed CAVLC Encoder for 1080p 60-Hz H.264 Codec,
SPLetters(15), No. 1, 2008, pp. 891-894.
IEEE DOI
0812
BibRef
Fan, C.P.,
Su, G.A.,
Efficient Low-Cost Sharing Design of Fast 1-D Inverse Integer Transform
Algorithms for H.264/AVC and VC-1,
SPLetters(15), No. 1, 2008, pp. 926-929.
IEEE DOI
0901
BibRef
Fan, C.P.,
Su, G.A.,
Efficient Fast 1-D 8x8 Inverse Integer Transform for VC-1
Application,
CirSysVideo(19), No. 4, April 2009, pp. 584-590.
IEEE DOI
0906
BibRef
Chao, Y.C.,
Wei, S.T.,
Liu, B.D.,
Yang, J.F.,
Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in
Compact H.264/AVC Decoder,
CirSysVideo(19), No. 1, January 2009, pp. 53-62.
IEEE DOI
0902
BibRef
Dang, P.P.[Philip P.],
Architecture of an application-specific processor for real-time
implementation of H.264/AVC sub-pixel interpolation,
RealTimeIP(4), No. 1, March 2009, pp. xx-yy.
Springer DOI
0903
BibRef
Urban, F.[Fabrice],
Nezan, J.F.[Jean-François],
Raulet, M.[Mickaël],
HDS, a real-time multi-DSP motion estimator for MPEG-4 H.264 AVC high
definition video encoding,
RealTimeIP(4), No. 1, March 2009, pp. xx-yy.
Springer DOI
0903
BibRef
Lin, Y.K.,
Ku, C.W.,
Li, D.W.,
Chang, T.S.,
A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264
Encoder,
CirSysVideo(19), No. 3, March 2009, pp. 432-436.
IEEE DOI
0903
BibRef
Celebi, A.[Anil],
Akbulut, O.[Orhan],
Urhan, O.[Oguzhan],
Hamzaoglu, I.[Ilker],
Erturk, S.[Sarp],
An All Binary Sub-Pixel Motion Estimation Approach
and its Hardware Architecture,
Consumer(54), No. 4, November 2008.
BibRef
0811
Parlak, M.[Mustafa],
Adibelli, Y.[Yusuf],
Hamzaoglu, I.[Ilker],
A Novel Computational Complexity and Power Reduction Technique
for H.264 Intra Prediction,
Consumer(54), No. 4, November 2008.
BibRef
0811
Hamzaoglu, I.[Ilker],
Tasdizen, O.[Ozgur],
Sahin, E.[Esra],
An Efficient H.264 Intra Frame Coder System,
Consumer(54), No. 4, November 2008.
BibRef
0811
Adibelli, Y.[Yusuf],
Parlak, M.[Mustafa],
Hamzaoglu, I.[Ilker],
A novel energy reduction technique for H.264 intra mode decision,
ICIP11(385-388).
IEEE DOI
1201
BibRef
Tasdizen, O.[Ozgur],
Hamzaoglu, I.[Ilker],
Recursive Dynamically Variable Step Search Motion Estimation Algorithm
for High Definition Video,
ICPR10(2354-2357).
IEEE DOI
1008
BibRef
Parlak, M.[Mustafa],
Hamzaoglu, I.[Ilker],
Low Power H.264 Deblocking Filter Hardware Implementations,
Consumer(54), No. 2, May 2008.
BibRef
0805
Schwalb, M.,
Ewerth, R.,
Freisleben, B.,
Fast Motion Estimation on Graphics Hardware for H.264 Video Encoding,
MultMed(11), No. 1, January 2009, pp. 1-10.
IEEE DOI
0905
BibRef
Lin, H.Y.[Heng-Yao],
Lu, Y.H.[Ying-Hong],
Liu, B.D.[Bin-Da],
Yang, J.F.[Jar-Ferr],
A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder,
MultMed(10), No. 1, January 2008, pp. 31-42.
IEEE DOI
0905
BibRef
Lin, H.Y.[Heng-Yao],
Wu, K.H.[Kuan-Hsien],
Liu, B.D.[Bin-Da],
Yang, J.F.[Jar-Ferr],
An Efficient VLSI Architecture for Transform-Based Intra Prediction in
H.264/AVC,
CirSysVideo(20), No. 6, June 2010, pp. 894-906.
IEEE DOI
1007
BibRef
Lou, J.,
Jagmohan, A.,
He, D.,
Lu, L.,
Sun, M.T.,
H.264 Deblocking Speedup,
CirSysVideo(19), No. 8, August 2009, pp. 1178-1182.
IEEE DOI
0909
BibRef
Bahari, A.,
Arslan, T.,
Erdogan, A.T.,
Low-Power H.264 Video Compression Architectures for Mobile
Communication,
CirSysVideo(19), No. 9, September 2009, pp. 1251-1261.
IEEE DOI
0909
BibRef
Yang, Y.C.,
Guo, J.I.,
High-Throughput H.264/AVC High-Profile CABAC Decoder for HDTV
Applications,
CirSysVideo(19), No. 9, September 2009, pp. 1395-1399.
IEEE DOI
0909
BibRef
Finchelstein, D.F.,
Sze, V.,
Chandrakasan, A.P.,
Multicore Processing and Efficient On-Chip Caching for H.264 and Future
Video Decoders,
CirSysVideo(19), No. 11, November 2009, pp. 1704-1713.
IEEE DOI
0912
BibRef
Chang, H.C.,
Chen, J.W.,
Wu, B.T.,
Su, C.L.,
Wang, J.S.,
Guo, J.I.,
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video
Applications,
CirSysVideo(19), No. 12, December 2009, pp. 1739-1754.
IEEE DOI
0912
BibRef
Yoo, K.[Kiwon],
Sohn, K.H.[Kwang-Hoon],
Hardware design of motion data decoding process for H.264/AVC,
SP:IC(25), No. 3, March 2010, pp. 208-223.
Elsevier DOI
1003
H.264/AVC; Motion vector derivation; Motion data decoding; Hardware
design; VLSI design.
BibRef
Yoo, K.[Kiwon],
Lee, J.H.[Jae-Hun],
Sohn, K.H.[Kwang-Hoon],
VLSI architecture design of motion vector processor for H.264/AVC,
ICIP08(1412-1415).
IEEE DOI
0810
BibRef
Hwangbo, W.,
Kyung, C.M.,
A Multitransform Architecture for H.264/AVC High-Profile Coders,
MultMed(12), No. 3, March 2010, pp. 157-167.
IEEE DOI
1003
BibRef
Lee, G.G.,
Lo, C.C.,
Chen, Y.C.,
Lin, H.Y.,
Wang, M.J.,
High-throughput low-cost VLSI architecture for
AVC/H.264 CAVLC decoding,
IET-IPR(4), No. 2, April 2010, pp. 81-91.
DOI Link
1003
BibRef
Tsai, A.C.[An-Chao],
Bharanitharan, K.,
Wang, J.F.[Jhing-Fa],
Yang, J.F.[Jar-Ferr],
Classified Multifilter Up-Sampling Algorithm in Spatial Scalability for
H.264/SVC Encoder,
CirSysVideo(20), No. 6, June 2010, pp. 861-869.
IEEE DOI
1007
BibRef
Chen, S.G.[Sheng-Gang],
Chen, S.M.[Shu-Ming],
Sun, S.W.[Shu-Wei],
P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the
Manycore Era,
CirSysVideo(20), No. 6, June 2010, pp. 920-924.
IEEE DOI
1007
Context based adaptive binary arithmetic coder. Poor parallelism.
BibRef
Wu, G.L.,
Chen, C.Y.,
Wu, T.H.,
Chien, S.Y.,
Efficient Spatial-Temporal Error Concealment Algorithm and Hardware
Architecture Design for H.264/AVC,
CirSysVideo(20), No. 11, November 2010, pp. 1409-1422.
IEEE DOI
1011
BibRef
Wu, G.L.,
Chen, C.Y.,
Chien, S.Y.,
Algorithm and Architecture Design of Image Inpainting Engine for Video
Error Concealment Applications,
CirSysVideo(21), No. 6, June 2011, pp. 792-803.
IEEE DOI
1101
BibRef
Wu, G.L.,
Wu, T.H.,
Chien, S.Y.,
Algorithm and Architecture Design of Perception Engine for Video Coding
Applications,
MultMed(13), No. 6, 2011, pp. 1181-1194.
IEEE DOI
1112
BibRef
Rhee, C.E.,
Jung, J.S.,
Lee, H.J.,
A Real-Time H.264/AVC Encoder With Complexity-Aware Time Allocation,
CirSysVideo(20), No. 12, December 2010, pp. 1848-1862.
IEEE DOI
1102
BibRef
Michell, J.A.[Juan A.],
Solana, J.M.[Jose M.],
Ruiz, G.A.[Gustavo A.],
A high-throughput ASIC processor for 8x8 transform coding in H.264/AVC,
SP:IC(26), No. 2, February 2011, pp. 93-104.
Elsevier DOI
1103
H.264/AVC; 8x8 integer cosine transform; Quantization; Transform
coding; ASIC processor
BibRef
Ruiz, G.A.,
Michell, J.A.,
An efficient VLSI processor chip for variable block size integer motion
estimation in H.264/AVC,
SP:IC(26), No. 6, July 2011, pp. 289-303.
Elsevier DOI
1101
H.264/AVC; Full search motion estimation; Variable block size motion
estimation (VBSME); VLSI architecture
BibRef
Boulakradeche, M.[Mohamed],
Ait-Aoudia, S.[Samy],
Towards a real-time video compression based on MPEG4 AVC/H.264,
IJCVR(2), No. 1, 2011, pp. 18-33.
DOI Link
1104
BibRef
Liu, Z.Y.[Zhen-Yu],
Zhou, J.W.[Jun-Wei],
Wang, D.S.[Dong-Sheng],
Ikenaga, T.[Takeshi],
Register Length Analysis and VLSI Optimization of VBS Hadamard
Transform in H.264/AVC,
CirSysVideo(21), No. 5, May 2011, pp. 601-610.
IEEE DOI
1105
BibRef
Xiao, Z.,
Baas, B.M.,
A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained
Many-Core System,
CirSysVideo(21), No. 7, July 2011, pp. 890-902.
IEEE DOI
1107
BibRef
Hamidouche, W.[Wassim],
Perrine, C.[Clency],
Pousset, Y.[Yannis],
Olivier, C.[Christian],
A solution to efficient power allocation for H.264/SVC video
transmission over a realistic MIMO channel using precoder designs,
JVCIR(22), No. 6, August 2011, pp. 563-574.
Elsevier DOI
1108
Optimal power allocation; H.264/SVC; JSCC; MIMO channels; Precoder
solutions; QoS precoder; E-dmin precoder; 3D-ray tracer
BibRef
Abot, J.[Julien],
Olivier, C.[Christian],
Perrine, C.[Clency],
Pousset, Y.[Yannis],
A link adaptation scheme optimized for wireless JPEG 2000 transmission
over realistic MIMO systems,
SP:IC(27), No. 10, November 2012, pp. 1066-1078.
Elsevier DOI
1211
JPWL image transmission; Link adaptation; CL-MIMO-OFDM; Unequal error
protection; Unequal power allocation; Adaptive modulation
BibRef
Mhamdi, M.[Marwa],
Perrine, C.[Clency],
Zribi, A.[Amin],
Pousset, Y.[Yannis],
Olivier, C.[Christian],
Bouallègue, A.[Ammar],
Soft decoding algorithms for optimized JPEG 2000 wireless
transmission over realistic MIMO-OFDM systems,
SP:IC(52), No. 1, 2017, pp. 41-53.
Elsevier DOI
1701
Cross layer PHY-APP
BibRef
Hamidouche, W.[Wassim],
Olivier, C.[Christian],
Pousset, Y.[Yannis],
Perrine, C.[Clency],
Optimal resource allocation for Medium Grain Scalable video
transmission over MIMO channels,
JVCIR(24), No. 3, April 2013, pp. 373-387.
Elsevier DOI
1303
Joint source-channel coding; Wireless video streaming; Optimal resource
allocation; H.264/SVC; Rate-distortion optimization; MIMO channels;
IEEE802.11n; QoS
BibRef
Abot, J.,
Nauge, M.,
Perrine, C.,
Larabi, C.,
Bergeron, C.,
Pousset, Y.,
Olivier, C.,
A robust content-based JPWL transmission over a realistic MIMO channel
under perceptual constraints,
ICIP11(3241-3244).
IEEE DOI
1201
BibRef
Ndili, O.[Obianuju],
Ogunfunmi, T.[Tokunbo],
Algorithm and Architecture Co-Design of Hardware-Oriented, Modified
Diamond Search for Fast Motion Estimation in H.264/AVC,
CirSysVideo(21), No. 9, September 2011, pp. 1214-1227.
IEEE DOI
1109
BibRef
Earlier:
Hardware-oriented Modified Diamond Search for motion estimation in
H.246/AVC,
ICIP10(749-752).
IEEE DOI
1009
BibRef
Ma, Z.[Zhan],
Hu, H.[Hao],
Wang, Y.[Yao],
On Complexity Modeling of H.264/AVC Video Decoding and Its Application
for Energy Efficient Decoding,
MultMed(13), No. 6, 2011, pp. 1240-1255.
IEEE DOI
1112
BibRef
Hu, H.[Hao],
Ma, Z.[Zhan],
Wang, Y.[Yao],
Optimization of spatial, temporal and amplitude resolution for
rate-constrained video coding and scalable video adaptation,
ICIP12(717-720).
IEEE DOI
1302
BibRef
Liao, Y.H.,
Li, G.L.,
Chang, T.S.,
A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC
Decoder,
CirSysVideo(22), No. 2, February 2012, pp. 272-281.
IEEE DOI
1202
BibRef
Matei, E.[Elena],
van Praet, C.[Christophe],
Bauwelinck, J.[Johan],
Cautereels, P.[Paul],
de Lumley, E.G.[Edith G.],
Novel data storage for H.264 motion compensation:
System Architecture and Hardware Implementation,
JIVP(2011), No. 1 2011, pp. xx-yy.
DOI Link
1203
BibRef
Huang, H.J.,
Fang, C.H.,
Fan, C.P.,
Very-large-scale integration design of a low-power and cost-effective
context-based adaptive variable length coding decoder for H.264/AVC
portable applications,
IET-IPR(6), No. 2, 2012, pp. 104-114.
DOI Link
1204
BibRef
Li, G.L.,
Chen, Y.C.,
Liao, Y.H.,
Hsu, P.Y.,
Wen, M.H.,
Chang, T.S.,
A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile
Decoder,
CirSysVideo(22), No. 4, April 2012, pp. 626-635.
IEEE DOI
1204
BibRef
Tu, T.H.[Tang-Hsun],
Hsueh, C.W.[Chih-Wen],
Wu, J.L.[Ja-Ling],
Batch-pipelining for multicore H.264 decoding,
JVCIR(23), No. 5, July 2012, pp. 742-752.
Elsevier DOI
1205
Parallelization; Pipelining; Batch; H.264; HEVC; Multicore;
Synchronization; Optimization
BibRef
Tsai, A.C.[An-Chao],
Bharanitharan, K.,
Wang, J.F.[Jhing-Fa],
Lee, K.I.[Kuan-I],
Effective Search Point Reduction Algorithm and its VLSI Design for HDTV
H.264/AVC Variable Block Size Motion Estimation,
CirSysVideo(22), No. 7, July 2012, pp. 981-988.
IEEE DOI
1208
BibRef
Liao, Y.H.,
Li, G.L.,
Chang, T.S.,
A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for
Ultra HD H.264/AVC Video,
CirSysVideo(22), No. 11, November 2012, pp. 1604-1610.
IEEE DOI
1211
BibRef
Werda, I.[Imen],
Dammak, T.[Taheni],
Grandpierre, T.[Thierry],
Ben Ayed, M.A.[Mohamed Ali],
Masmoudi, N.[Nouri],
Real-time H.264/AVC baseline decoder implementation on TMS320C6416,
RealTimeIP(7), No. 4, December 2012, pp. 215-232.
WWW Link.
1212
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Zatt, B.[Bruno],
de L. Silva, L.M.[Leandro M.],
Azevedo, A.[Arnaldo],
Agostini, L.[Luciano],
Susin, A.[Altamiro],
Bampi, S.[Sergio],
A reduced memory bandwidth and high throughput HDTV motion compensation
decoder for H.264/AVC High 4:2:2 profile,
RealTimeIP(8), No. 1, March 2013, pp. 127-140.
WWW Link.
1303
BibRef
Pastuszak, G.,
Jakubowski, M.,
Adaptive Computationally Scalable Motion Estimation for the Hardware
H.264/AVC Encoder,
CirSysVideo(23), No. 5, May 2013, pp. 802-812.
IEEE DOI
1305
BibRef
Seo, J.H.[Jung-Han],
Jo, H.H.[Hyun-Ho],
Sim, D.G.[Dong-Gyu],
Kim, D.H.[Doo-Hyun],
Song, J.H.[Joon-Ho],
Fast CAVLD of H.264/AVC on bitstream decoding processor,
JIVP(2013), No. 1, 2013, pp. 23.
DOI Link
1305
BibRef
Min, K.Y.[Kyung-Yeon],
Sim, D.G.[Dong-Gyu],
Adaptive distributed video coding with motion vectors through a back
channel,
JIVP(2013), No. 1, 2013, pp. 22.
DOI Link
1305
BibRef
Min, K.Y.[Kyung-Yeon],
Lim, W.[Woong],
Nam, J.[Junghak],
Sim, D.G.[Dong-Gyu],
Bajic, I.V.[Ivan V.],
Distributed video coding supporting hierarchical GOP structures with
transmitted motion vectors,
JIVP(2015), No. 1, 2015, pp. 12.
DOI Link
1506
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Gao, G.[Gugang],
Cao, P.[Peng],
Yang, J.[Jun],
Shi, L.X.[Long-Xing],
Parallelism Analysis of H.264 Decoder and Realization on a
Coarse-Grained Reconfigurable SoC,
IEICE(E96-D), No. 8, August 2013, pp. 1654-1666.
WWW Link.
1308
BibRef
Vanam, R.[Rahul],
Riskin, E.A.[Eve A.],
Ladner, R.E.[Richard E.],
Hemami, S.S.[Sheila S.],
Fast algorithms for designing nearly optimal lookup tables for
complexity control of the H.264 encoder,
SIViP(7), No. 5, September 2013, pp. 991-1003.
Springer DOI
1309
BibRef
Zhu, C.[Chuang],
Jia, H.Z.[Hui-Zhu],
Zhang, S.H.[Shang-Hang],
Huang, X.F.[Xiao-Feng],
Xie, X.D.[Xiao-Dong],
Gao, W.[Wen],
On a Highly Efficient RDO-Based Mode Decision Pipeline Design for AVS,
MultMed(15), No. 8, December 2013, pp. 1815-1829.
IEEE DOI
1402
CMOS logic circuits
BibRef
Ko, Y.S.[Young-Sub],
Yi, Y.M.[Young-Min],
Ha, S.H.[Soon-Hoi],
An efficient parallelization technique for x264 encoder on
heterogeneous platforms consisting of CPUs and GPUs,
RealTimeIP(9), No. 1, March 2014, pp. 5-18.
WWW Link.
1403
BibRef
Fan, C.P.[Chih-Peng],
Chang, C.W.[Chia-Wei],
Hsu, S.J.[Shun-Ji],
Cost-Effective Hardware-Sharing Design of Fast Algorithm Based
Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4,
AVS, and VC-1 Video Encoding and Decoding Applications,
CirSysVideo(24), No. 4, April 2014, pp. 714-720.
IEEE DOI
1405
adaptive codes
BibRef
Wang, B.,
Alvarez-Mesa, M.,
Chi, C.C.,
Juurlink, B.,
Parallel H.264/AVC Motion Compensation for GPUs Using OpenCL,
CirSysVideo(25), No. 3, March 2015, pp. 525-531.
IEEE DOI
1503
Decoding
BibRef
Baaklini, E.[Elias],
Rethinagiri, S.[Santhosh],
Sbeity, H.[Hassan],
Niar, S.[Smail],
Scalable row-based parallel H.264 decoder on embedded multicore
processors,
SIViP(9), No. 1 Supp, December 2015, pp. 57-71.
Springer DOI
1601
BibRef
Aksehir, Y.[Yusuf],
Erdayandi, K.[Kamil],
Ozcan, T.Z.[Tevfik Zafer],
Hamzaoglu, I.[Ilker],
A low energy adaptive motion estimation hardware for H.264 multiview
video coding,
RealTimeIP(15), No. 1, June 2018, pp. 3-12.
Springer DOI
1806
BibRef
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Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
HEVC Coding, Decoding: Hardware and Systems .