Co Author Listing * Design of New Optimized Architecture Processor for DWT
* Efficient and high-performance pedestrian detector implementation for intelligent vehicles
* efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000, An
* efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding, An
* efficient pass-parallel architecture for embedded block coder in JPEG 2000, An
* Embedded Real-Time Video Processing System on FPGA
* Fast CU partition-based machine learning approach for reducing HEVC complexity
* FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM, An
* Generalized Fourier Descriptors with Applications to Objects Recognition in SVM Context
* Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances
* Optimisation of HEVC motion estimation exploiting SAD and SSD GPU-based implementation
Includes: Atri, M.[Mohamed] Atri, M.
11 for Atri, M.
Index for "a"