5.5.10 Motion and Video Coding: Hardware and Systems

Chapter Contents (Back)
Compression. Hardware. Architectures. Compression, Video. See also Hardware and Architecture for Coding.

Yang, K.M.[Kun-Min], Legall, D.J.[Didier J.],
Hardware design of a motion video decoder for 1-1.5 Mbps rate applications,
SP:IC(2), No. 2, August 1990, pp. 117-126.
WWW Link. 0001
Modular hardware design; evaluation of hardware complexity; compatibility with other coding algorithm BibRef

Wu, L.[Lancelot], Yang, K.M.[Kun-Min],
Circuit implementation of block matching algorithm,
US_Patent4,897,720, Jan 30, 1990
WWW Link. BibRef 9001

Yang, K.M.[Kun-Min],
Circuit implementation of block matching algorithm with fractional precision,
US_Patent4,937,666, Jun 26, 1990
WWW Link. BibRef 9006

de Lameillieure, J.L.P.[Jan L.P.], Bruyland, I.[Ignace],
Single stage 280 Mbit/s coding of HDTV using HDPCM with a vector quantizer based on masking functions,
SP:IC(2), No. 3, October 1990, pp. 279-289.
WWW Link. 0001
BibRef

Hamilton, E.R.[Eric R.], Douglas, J.L.[John L.], Widergren, J.B.[Jeffrey B.],
Computer-based video compression system,
US_Patent4,897,717, 01/30/1990.
HTML Version. BibRef 9001

Adolph, D.[Dirk], Buschmann, R.[Ralf],
1.15 Mbit/s coding of video signals including global motion compensation,
SP:IC(3), No. 2-3, June 1991, pp. 259-274.
WWW Link. 0001
BibRef

Brofferio, S.C., Mastronardi, G., Rampa, V.,
A migrating data-driven architecture for multidimensional signal processing,
SP:IC(3), No. 2-3, June 1991, pp. 249-257.
Elsevier DOI 0001
BibRef

Sawada, K.[Katsutoshi], Yashima, Y.[Yoshiyuki], Sakai, H.[Hiroshi],
An HDTV bit-rate reduction codec at the STM-1 rate of SDH,
SP:IC(4), No. 4-5, August 1992, pp. 345-358.
WWW Link. 0001
HDTV; bit-rate reduction; DCT; STM-1 BibRef

Matsumoto, S.[Shuichi], Murakami, H.[Hitomi],
120/140 Mbit/s portable HDTV codec and its transmission performance in a field trial via INTELSAT satellite,
SP:IC(4), No. 4-5, August 1992, pp. 359-377.
WWW Link. 0001
HDTV; intrafield DPCM; noise shaping; field trial; BER; link budget BibRef

Matsumoto, S.[Shuichi], Murakami, H.[Hitomi], Murakami, H.[Hitomi], Yamamoto, H.[Hideo],
Adaptive predictive coding system for television signals,
US_Patent4,546,386, 10/08/1985.
HTML Version. BibRef 8510
Earlier:
Inter-frame adaptive prediction system for television signals,
US_Patent4,437,119, 03/13/1984.
HTML Version. BibRef

Ohtsuka, Y.[Yoshimichi], Nakasu, E.[Eisuke], Shishikui, Y.[Yoshiaki], Imaizumi, H.[Hiroyuki], Nakanishi, H.[Hiroshi],
Development of 135 Mbit/s HDTV codec,
SP:IC(4), No. 4-5, August 1992, pp. 379-387.
WWW Link. 0001
HDTV; DCT; motion compensation; B2 code; CCIR Rec.723 BibRef

Okubo, S.[Sakae], Wada, M.[Masahiro], Carr, M.D.[Mike D.], Tabatabai, A.J.[Ali J.],
Hardware trials for verifying recommendation H.261 on p*64 kbit/s video codec,
SP:IC(3), No. 1, February 1991, pp. 71-78.
WWW Link. 0001
Visual telephone service; Recommendation H.261 BibRef

Jozawa, H.[Hirohisa], Shimizu, A.[Atsushi], Kamikura, K.[Kazuto], Watanabe, H.[Hiroshi],
Predictive encoding and decoding methods of video data,
US_Patent6,785,331, Aug 31, 2004
WWW Link. BibRef 0408

Watanabe, H.[Hiroshi], Suzuki, Y.[Yutaka],
64 kbit/s Video coding algorithm using adaptive gain/shape vector quantization,
SP:IC(1), No. 2, October 1990, pp. 87-102.
WWW Link. 0001
High efficiency video coding; hybrid coding; vector quantization; tree search codebook; gain/shape vector quantization; motion compensation; conditional replenishment; videoconferencing; videophone; video codec; ISDN terminal BibRef

Grotz, K.[Karlheinz], Mayer, J.U.[Joerg U.], Suessmeier, G.K.[Georg K.],
A 64 kbit/s Videophone codec with forward analysis and control,
SP:IC(1), No. 2, October 1990, pp. 103-115.
WWW Link. 0001
Displacement estimation by gradient method; motion compensation with subpel aaccuracy; noise adaptation; forward control BibRef

Hoek, C.[Cornelis], Heiss, R.[Rainer], Mueller, D.[Detlef],
An array processor approach for low bit rate video coding,
SP:IC(1), No. 2, October 1990, pp. 213-223.
WWW Link. 0001
Hybrid codec; videocoding; array processor; SIMD BibRef

Balestri, M., Rinaudo, A.,
A general architecture of video codec for real time communication at 64 kbit/s,
SP:IC(1), No. 2, October 1990, pp. 239-243.
WWW Link. 0001
Photovideotex; videophone; video coding; parallel processing BibRef

Chen, L.G.[Liang-Gee], Liu, Y.C.[Yuan-Chen],
A high quality MC-OBTC Codec for video signal processing,
CirSysVideo(4), No. 1, February 1994, pp. 92-98.
IEEE Top Reference. 0206
BibRef

Chang, S.F., Messerschmitt, D.G.,
Designing high-throughput VLC decoder. I. Concurrent VLSI architectures,
CirSysVideo(2), No. 2, June 1992, pp. 187-196.
IEEE Top Reference. 0206
BibRef

Lin, H.D., Messerschmitt, D.G.,
Designing a high-throughput VLC decoder. II. Parallel decoding methods,
CirSysVideo(2), No. 2, June 1992, pp. 197-206.
IEEE Top Reference. 0206
BibRef

Frimout, E.D., Driessen, I.N., Deprettere, E.F.,
Parallel architecture for a pel-recursive motion estimation algorithm,
CirSysVideo(2), No. 2, June 1992, pp. 159-168.
IEEE Top Reference. 0206
BibRef

Jeschke, H., Gaedke, K., Pirsch, P.,
Multiprocessor performance for real-time processing of video coding applications,
CirSysVideo(2), No. 2, June 1992, pp. 221-230.
IEEE Top Reference. 0206
BibRef

Villasenor, J.D., Jones, C., Schoner, B.,
Video communications using rapidly reconfigurable hardware,
CirSysVideo(5), No. 6, December 1995, pp. 565-567.
IEEE Top Reference. 0206
BibRef

Tsern, E.K., Meng, T.H.,
A Low-Power Video-Rate Pyramid VQ Decoder,
SolidCir(31), No. 11, November 1996, pp. 1789-1794. 9611
BibRef

Lin, H.D., Anesko, A., Petryna, B.,
A 14-GOPs Programmable Motion Estimator for H.26X Video Coding,
SolidCir(31), No. 11, November 1996, pp. 1742-1750. 9611
BibRef

Huang, H.C., Wu, J.L.,
New-Generation of Real-Time Software-Based Video Coder: Popular-Video-Coder-II (PVC-II),
Consumer(42), No. 4, November 1996, pp. 963-973. 9701
BibRef

Hsiau, D.Y., Wu, J.L.,
Real Time PC Based Software Implementation of H.261 Video Codec,
Consumer(43), No. 4, November 1997, pp. 1234-1244. 9801
BibRef

Schuster, G.M., Katsaggelos, A.K.,
A Video Compression Scheme with Optimal Bit Allocation Among Segmentation, Motion, and Residual Error,
IP(6), No. 11, November 1997, pp. 1487-1502.
IEEE DOI 9710
BibRef

Wang, H.H.[Hao-Hong], Schuster, G.M., Katsaggelos, A.K.,
Object-based video compression scheme with optimal bit allocation among shape, motion and texture,
ICIP03(III: 785-788).
IEEE DOI 0312
BibRef

Schuster, G.M., Katsaggelos, A.K.,
An Optimal Quadtree-based Motion Estimation and Motion-compensated Interpolation Scheme for Video Compression,
IP(7), No. 11, November 1998, pp. 1505-1523.
IEEE DOI BibRef 9811

Lu, Y., Yong, Z., Yao, Q.D.,
Hierarchical Motion Estimation Algorithms with Especially Low Hardware Costs,
Consumer(44), No. 1, February 1998, pp. 125-129. 9804
BibRef

Liu, P.C., Chang, W.T., Shen, W.Z.,
Combinative Motion Estimation Algorithm and the Corresponding Architecture for Complex Motion Phenomenon,
Consumer(44), No. 1, February 1998, pp. 108-116. 9804
BibRef

Kweh, T.H., Eryurtlu, F., Kondoz, A.M.,
Closed Loop Motion Compensation for Video Coding Standards,
VISP(144), No. 4, August 1997, pp. 227-232. 9806
BibRef

Boo, K.J., Bose, N.K.,
A Motion Compensated Spatiotemporal Filter for Image Sequences with Signal Dependent Noise,
CirSysVideo(8), No. 3, June 1998, pp. 287-298.
IEEE Top Reference. 9806
BibRef

Schutten, R.J., de Haan, G.,
Real-Time 2-3 Pull-Down Elimination Applying Motion Estimation/Compensation in a Programmable Device,
Consumer(44), No. 3, August 1998, pp. 930-938. 9810
BibRef

Chiu, Y.J., Berger, T.,
Software-Only Videocodec Using Pixelwise Conditional Differential Replenishment and Perceptual Enhancements,
CirSysVideo(9), No. 4, April 1999, pp. 438.
IEEE Top Reference. BibRef 9904

Huang, H.C.[Ho-Chao], Wu, J.L.[Ja-Ling],
Real-time software-based moving picture coding (SBMPC) system,
SP:IC(6), No. 2, May 1994, pp. 173-187.
WWW Link. BibRef 9405

Choi, S.H., Park, K.T.,
High-speed moving picture coding using adaptively load balanced multiprocessor system,
SP:IC(8), No. 2, March 1996, pp. 113-130.
WWW Link. BibRef 9603

Kwak, J.S.[Jin Suk], Lee, K.W.[Kang Whan], Kim, J.W.[Jin Woong], Lee, Y.S.[Young Sun], Jeong, J.H.[Joo Hong], Ahn, C.T.[Chie Teuk],
Apparatus for estimating a half-pel motion in a video compression method,
US_Patent5,694,179, Dec 2, 1997
WWW Link. BibRef 9712

Choi, Y.[Yunjung], Cho, S.H.[Suk-Hee], Lee, J.W.[Jinh-Wan], Ahn, C.T.[Chie-Teuk],
Field-based stereoscopic video codec for multiple display methods,
ICIP02(II: 253-256).
IEEE DOI 0210
BibRef

Choi, J.,
Distortion Policy of Buffer-Constrained Rate Control for Real-Time VBR Coders,
IP(8), No. 4, April 1999, pp. 537-547.
IEEE DOI BibRef 9904

Charot, F., Le Fol, G., Lemonnier, P., Wagner, C., Barzic, R., Bouville, C.,
Toward Hardware Building Blocks for Software-Only Real-Time Video Processing: The MOVIE Approach,
CirSysVideo(9), No. 6, September 1999, pp. 882.
IEEE Top Reference. BibRef 9909

Li, J.H., Ling, N.,
Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder,
CirSysVideo(9), No. 5, August 1999, pp. 727.
IEEE Top Reference. BibRef 9908

Kim, C.S., Kim, R.C., Lee, S.U.,
An Error Detection and Recovery Algorithm for Compressed Video Signal Using Source Level Redundancy,
IP(9), No. 2, February 2000, pp. 209-219.
IEEE DOI 0003
BibRef

Cheung, G., Zakhor, A.[Avideh],
Bit Allocation for Joint Source/Channel Coding of Scalable Video,
IP(9), No. 3, March 2000, pp. 340-356.
IEEE DOI 0003
BibRef
Earlier:
Joint Source/Channel Coding of Scalable Video over Noisy Channels,
ICIP96(III: 767-770).
IEEE DOI 9610
Wireless BibRef

Lentola, L., Cortelazzo, G.M., Malavasi, E., Baschirotto, A.,
Design of SC Filters for Video Applications,
CirSysVideo(10), No. 1, February 2000, pp. 14.
IEEE Top Reference. 0003
BibRef

Miyake, J., Urano, M., Inoue, G., Yano, J., Tsubata, S., Nishiyama, T., Yamaguchi, S.,
Architecture of 23GOPs Video Signal Processor with Programmable Systolic Array,
CirSysSignal(45), No. 9, September 1998, pp. 1272-1278. 9809
BibRef

Oh, S.H., Han, S.H., Kang, B., Lee, M.K.,
An ASIC Implementation of an Optimized Digital Video Encoder,
Consumer(44), No. 3, August 1998, pp. 1097-1102. 9810
BibRef

Dutta, S., O'Connor, K.J., Wolf, W., Wolfe, A.,
A Design Study of a 0.25-Mu-M Video Signal Processor,
CirSysVideo(8), No. 4, August 1998, pp. 501-519.
IEEE Top Reference. 9809
BibRef

Mattavelli, M., Brunetton, S.,
Implementing Real-Time Video Decoding On Multimedia Processors by Complexity Prediction Techniques,
Consumer(44), No. 3, August 1998, pp. 760-767. 9810
BibRef

Yu, G.S., Liu, M.M.K., Marcellin, M.W.,
POCS-Based Error Concealment for Packet Video Using Multiframe Overlap Information,
CirSysVideo(8), No. 4, August 1998, pp. 422-434.
IEEE Top Reference. 9809
BibRef

Jeon, J.H., Park, Y.S., Park, H.W.,
A Fast Variable-Length Decoder Using Plane Separation,
CirSysVideo(10), No. 5, August 2000, pp. 806-812.
IEEE Top Reference. 0008
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Lee, C.S.[Chul Soo], Park, J.H.[Joon-Hong], Yoon, D.S.[Doo-Soo], Jeon, J.[JaeHo], Park, H.W.[Hyun-Wook], Yeo, J.H.[Ji Hee], Lee, J.H.[Jong Hwa],
A real-time encoding and decoding system for nonlinear HDTV editor,
IJIST(11), No. 2, 2000, pp. 152-157. 0008
BibRef

Lee, W.S., Pickering, M.R., Frater, M.R., Arnold, J.F.,
A Robust Codec for Transmission of Very Low Bit-Rate Video over Channels with Bursty Errors,
CirSysVideo(10), No. 8, December 2000, pp. 1403-1412.
IEEE Top Reference. 0012
BibRef
Earlier: A1, A3, A2, A4:
A Diversity-Based Scheme for Reducing Error Propagation in Video,
ICIP97(III: 582-585).
IEEE DOI BibRef

Leung, K.K., Yung, N.H.C., Cheung, P.Y.S.,
Parallelization Methodology for Video Coding: An Implementation on the TMS320C80,
CirSysVideo(10), No. 8, December 2000, pp. 1413-1425.
IEEE Top Reference. 0012
BibRef

Shieh, B.J., Lee, Y.S., Lee, C.Y.,
A High-Throughput Memory-Based VLC Decoder with Codeword Boundary Prediction,
CirSysVideo(10), No. 8, December 2000, pp. 1514-1521.
IEEE Top Reference. 0012
BibRef

Monro, D.M.[Donald Martin], Nicholls, J.A.[Jeremy Andrew],
Object-oriented video system,
US_Patent6,078,619, Jun 20, 2000
WWW Link. for compression BibRef 0006

Yung, N.H.C., Leung, K.K.,
Spatial and Temporal Data Parallelization of the H.261 Video Coding Algorithm,
CirSysVideo(11), No. 1, January 2001, pp. 91-104.
IEEE Top Reference. 0101
BibRef

Shieh, B.J.[Bai-Jue], Lee, Y.S.[Yew-San], Lee, C.Y.[Chen-Yi],
A new approach of group-based VLC codec system with full table programmability,
CirSysVideo(11), No. 2, February 2001, pp. 210-221.
IEEE Top Reference. 0104
BibRef

Bystrom, M., Kaiser, S., Kopansky, A.,
Soft source decoding with applications,
CirSysVideo(11), No. 10, October 2001, pp. 1108-1120.
IEEE Top Reference. 0110
BibRef

Kim, H.[Hansoo], Park, I.C.[In-Cheol],
High-performance and low-power memory-interface architecture for video processing applications,
CirSysVideo(11), No. 11, November 2001, pp. 1160-1170.
IEEE Top Reference. 0111
BibRef

Chen, W.S.[Wen-Shiung], Peng, Y.Y.[Yuan-Yu], Chang, Y.T.[Yung-Tsang], Wang, J.T.[Jen-Tse],
Design and implementation of real-time software-based H.261 video codec,
IJIST(12), No. 2, 2002, pp. 73-83.
WWW Link. 0205
BibRef

Wei, S.W., Wei, C.H.,
A high-speed real-time binary BCH decoder,
CirSysVideo(3), No. 2, April 1993, pp. 138-147.
IEEE Top Reference. 0206
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Luo, J.H.[Jeng-Hung], Wang, C.N.[Chung-Neng], Chiang, T.[Tihao],
A novel all-binary motion estimation (ABME) with optimized hardware architectures,
CirSysVideo(12), No. 8, August 2002, pp. 700-712.
IEEE Top Reference. 0208
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Panusopone, K., Baylon, D.M.,
An analysis and efficient implementation of half-pel motion estimation,
CirSysVideo(12), No. 8, August 2002, pp. 724-729.
IEEE Top Reference. 0208
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Lin, W., Panusopone, K., Baylon, D.M., Sun, M.T.,
A Computation Control Motion Estimation Method for Complexity-Scalable Video Coding,
CirSysVideo(20), No. 11, November 2010, pp. 1533-1543.
IEEE DOI 1011
BibRef

Tung, Y.S.[Yi-Shin], Wu, J.L.[Ja-Ling], Hsiao, P.K.[Po-Kang], Huang, K.L.[Kan-Li],
An efficient streaming and decoding architecture for stored fgs video,
CirSysVideo(12), No. 8, August 2002, pp. 730-735.
IEEE Top Reference. 0208
BibRef

Li, Z.G., Zhu, C., Ling, N., Yang, X.K., Feng, G.N., Wu, S., Pan, F.,
A unified architecture for real-time video-coding systems,
CirSysVideo(13), No. 6, June 2003, pp. 472-487.
IEEE Abstract. 0307
BibRef

Caetano, R.[Rogério], da Silva, E.A.B.[Eduardo A.B.],
A bit allocation scheme for a class of embedded wavelet video encoders,
JVCIR(14), No. 2, June 2003, pp. 136-149.
WWW Link. 0306
BibRef

Zhao, Y.F.[Ya-Fan], Richardson, I.E.G.[Iain E.G.],
Macroblock classification for complexity management of video encoders,
SP:IC(18), No. 9, October 2003, pp. 801-811.
WWW Link. 0310
BibRef
Earlier: A2, A1:
Video encoder complexity reduction by estimating skip mode distortion,
ICIP04(I: 103-106).
IEEE DOI 0505
BibRef

Tatas, K., Dasygenis, M., Kroupis, N., Argyriou, A.[Antonios], Soudris, D., Thanailakis, A.,
Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms,
RealTimeImg(9), No. 6, December 2003, pp. 371-386.
WWW Link. 0401
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Yen, J.C., Chang, F.J., Chang, S.[Shyang],
A new architecture for motion-compensated image coding,
PR(25), No. 4, April 1992, pp. 357-366.
WWW Link. 0401
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Li, T.[Tang],
Computation reduction for standard-based video encoders based on the energy preservation property of DCT,
SP:IC(19), No. 5, May 2004, pp. 457-464.
WWW Link. 0405
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Tanskanen, J.K., Sihvo, T., Niittylahti, J.,
Byte and Modulo Addressable Parallel Memory Architecture for Video Coding,
CirSysVideo(14), No. 11, November 2004, pp. 1270-1276.
IEEE Abstract. 0411
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Choi, B.D.[Byeong-Doo], Choi, K.S.[Kang-Sun], Hwang, M.C.[Min-Cheol], Cho, J.K.[Jun-Ki], Ko, S.J.[Sung-Jea],
Real-time DSP implementation of motion: JPEG2000 using overlapped block transferring and parallel-pass methods,
RealTimeImg(10), No. 5, October 2004, pp. 277-284.
WWW Link. 0501
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Choi, B.D.[Byeong-Doo], Han, J.W.[Jong-Woo], Ko, S.J.[Sung-Jea],
Irregular-Grid-Overlapped Block Motion Compensation and its Practical Application,
CirSysVideo(19), No. 8, August 2009, pp. 1221-1226.
IEEE DOI 0909
BibRef

Choi, B.D.[Byeong-Doo], Han, J.W.[Jong-Woo], Jung, S.W.[Seung-Won], Nam, J.H.[Ju-Hun], Ko, S.J.[Sung-Jea],
Overlapped Block Motion Compensation Based on Irregular Grid,
ICIP06(1085-1088).
IEEE DOI 0610
BibRef

Feng, W.[Wei], Kassim, A.A.[Ashraf A.], Tham, C.K.[Chen-Khong],
A scalable video codec for layered video streaming,
RealTimeImg(10), No. 5, October 2004, pp. 297-305.
WWW Link. 0501
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Yang, C.L., Tseng, H.W., Ho, C.C., Wu, J.L.,
Software-Controlled Cache Architecture for Energy Efficiency,
CirSysVideo(15), No. 5, May 2005, pp. 634-644.
IEEE Abstract. 0505
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Chen, T.F., Hsu, C.M., Wu, S.R.,
Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words,
CirSysVideo(15), No. 5, May 2005, pp. 659-672.
IEEE Abstract. 0505
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Ravasi, M., Mattavelli, M.,
High-Abstraction Level Complexity Analysis and Memory Architecture Simulations of Multimedia Algorithms,
CirSysVideo(15), No. 5, May 2005, pp. 673-684.
IEEE Abstract. 0505
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Shen, G., Gao, G.P., Li, S., Shum, H.Y., Zhang, Y.Q.,
Accelerate Video Decoding With Generic GPU,
CirSysVideo(15), No. 5, May 2005, pp. 685-693.
IEEE Abstract. 0505
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Guevorkian, D., Launiainen, A., Lappalainen, V., Liuha, P., Punkka, K.,
A Method for Designing High-Radix Multiplier-Based Processing Units for Multimedia Applications,
CirSysVideo(15), No. 5, May 2005, pp. 716-725.
IEEE Abstract. 0505
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Wu, C.B., Yao, C.Y., Liu, B.D., Yang, J.F.,
DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation,
CirSysVideo(15), No. 5, May 2005, pp. 694-703.
IEEE Abstract. 0505
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Li, P., Veeravalli, B., Kassim, A.A.,
Design and Implementation of Parallel Video Encoding Strategies Using Divisible Load Analysis,
CirSysVideo(15), No. 9, September 2005, pp. 1098-1112.
IEEE DOI 0509
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Chelladurai, P.S.[Paul Sathya], Ahmed, A.[Arshad], Nandy, S.K.[Soumitra Kumar],
Method for efficient low power motion estimation of a video frame sequence,
US_Patent6,968,010, Nov 22, 2005
WWW Link. BibRef 0511

Kwon, D.N., Driessen, P.F., Basso, A., Agathoklis, P.,
Performance and Computational Complexity Optimization in Configurable Hybrid Video Coding System,
CirSysVideo(16), No. 1, January 2006, pp. 31-42.
IEEE DOI 0601
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Balam, S., Schonfeld, D.,
Associative processors for video coding applications,
CirSysVideo(16), No. 2, February 2006, pp. 241-250.
IEEE DOI 0604
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Chen, C.Y., Huang, C.T., Chen, Y.H., Chen, L.G.,
Level C+ Data Reuse Scheme for Motion Estimation With Corresponding Coding Orders,
CirSysVideo(16), No. 4, April 2006, pp. 553-558.
IEEE DOI 0605
BibRef

Sayed, M., Badawy, W.,
An Affine-Based Algorithm and SIMD Architecture for Video Compression With Low Bit-Rate Applications,
CirSysVideo(16), No. 4, April 2006, pp. 457-471.
IEEE DOI 0605
BibRef

Akil, M., Perroton, L., Grandpierre, T.,
FPGA-based architecture for hardware compression/decompression of wide format images,
RealTimeIP(1), No. 2, December 2006, pp. 163-170.
Springer DOI 0001
BibRef

Chang, Y.W.[Yu-Wei], Cheng, C.C.[Chih-Chi], Chen, C.C.[Chun-Chia], Fang, H.C.[Hung-Chi], Chen, L.G.[Liang-Gee],
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory,
CirSysVideo(17), No. 4, April 2007, pp. 398-406.
IEEE DOI 0705
BibRef

François, E., Viéron, J., Bottreau, V.,
Interlaced Coding in SVC,
CirSysVideo(17), No. 9, September 2007, pp. 1136-1148.
IEEE DOI 0711
Scalable Video Codec BibRef

Tseng, P., Chang, Y., Huang, Y., Fang, H., Huang, C., Chen, L.,
Advances in Hardware Architectures for Image and Video Coding: A Survey,
PIEEE(93), No. 1, January 2005, pp. 184-197.
IEEE DOI 0501
Survey, Compression. BibRef

Kumura, T.[Takahiro], Kayama, N.[Norio], Shionoya, S.[Shinichi], Kumagiri, K.[Kazuo], Kusano, T.[Takao], Yoshida, M.[Makoto], Ikekawa, M.[Masao], Kuroda, I.[Ichiro], Nishitani, T.[Takao],
Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core,
IEICE(E88-D), No. 6, June 2005, pp. 1224-1230.
DOI Link 0506
BibRef

Brill, F.Z.[Frank Z.], Flinchbaugh, B.E.[Bruce E.],
Method and apparatus for compressing image information,
US_Patent6,937,651, Aug 30, 2005
WWW Link. BibRef 0508

Akyol, E.[Emrah], van der Schaar, M.[Mihaela],
Compression-Aware Energy Optimization for Video Decoding Systems With Passive Power,
CirSysVideo(18), No. 9, September 2008, pp. 1300-1306.
IEEE DOI 0810
BibRef
Earlier:
Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding Systems,
ICIP07(VI: 477-480).
IEEE DOI 0709
BibRef

Lim, Y.H.[Yo-Han], Kang, J.S.[Jung-Sun],
An efficient architecture of bitplane coding with high frame rate for VC-1,
SP:IC(23), No. 9, October 2008, pp. 692-698.
WWW Link. 0810
VC-1; WMV-9; Video coding; Bitplane coding BibRef

Yoshitome, T.[Takeshi], Nakamura, K.[Ken], Naganuma, J.[Jiro], Yashima, Y.[Yoshiyuki],
A Flexible Video CODEC System for Super High Resolution Video,
IEICE(E91-D), No. 11, November 2008, pp. 2709-2717.
DOI Link 0804
BibRef

Onishi, T.[Takayuki], Nakamura, K.[Ken], Yoshitome, T.[Takeshi], Naganuma, J.[Jiro],
A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV,
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DOI Link 0804
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Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System,
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IEEE DOI 0902
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IEEE DOI 0904
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Error Resilience in Current Distributed Video Coding Architectures,
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Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client,
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IEEE DOI 0905
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And:
Distortion estimates for adaptive temporal decompositions of video under displacement errors and quantization noise,
ICIP11(3701-3704).
IEEE DOI 1201
Adaptive signal decompositions; Lifting scheme; Distortion estimation BibRef

Zhang, X.M.[Xiong-Ming], Cheng, L.Z.[Li-Zhi], Lu, H.Z.[Huan-Zhang],
Low memory implementation of generic hierarchical transforms for parent-children tree (PCT) production and its application in image compression,
SP:IC(24), No. 5, May 2009, pp. 384-396.
Elsevier DOI 0905
Image compression; Hierarchical transform; Low-memory implementation; Parent-children tree BibRef

Guo, L.W.[Li-Wei], Au, O.C.[Oscar C.], Ma, M.Y.[Meng-Yao], Liang, Z., Wong, P.H.W.,
A Novel Analytic Quantization-Distortion Model for Hybrid Video Coding,
CirSysVideo(19), No. 5, May 2009, pp. 627-641.
IEEE DOI 0906
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Wang, S.H., Tai, S.H., Chiang, T.,
A Low-Power and Bandwidth-Efficient Motion Estimation IP Core Design Using Binary Search,
CirSysVideo(19), No. 5, May 2009, pp. 760-765.
IEEE DOI 0906
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Lee, D., Kim, H., Rahimi, M., Estrin, D., Villasenor, J.D.,
Energy-Efficient Image Compression for Resource-Constrained Platforms,
IP(18), No. 9, September 2009, pp. 2100-2113.
IEEE DOI 0909
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Kontorinis, N., Andreopoulos, Y., van der Schaar, M.,
Statistical Framework for Video Decoding Complexity Modeling and Prediction,
CirSysVideo(19), No. 7, July 2009, pp. 1000-1013.
IEEE DOI 0909
Analysis of the time cost of different aspects. BibRef

Shim, H.J.[Hee-Jun], Kyung, C.M.[Chong-Min],
Selective Search Area Reuse Algorithm for Low External Memory Access Motion Estimation,
CirSysVideo(19), No. 7, July 2009, pp. 1044-1050.
IEEE DOI 0909
To reduce onchip memory requirements. BibRef

Tian, X., Le, T.M., Jiang, X., Lian, Y.,
Full RDO-Support Power-Aware CABAC Encoder With Efficient Context Access,
CirSysVideo(19), No. 9, September 2009, pp. 1262-1273.
IEEE DOI 0909
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Pang, Y.[Yi], Sun, L.F.[Li-Feng], Wen, J.T.[Jiang-Tao], Zhang, F.Y.[Feng-Yan], Hu, W.D.[Wei-Dong], Feng, W.[Wei], Yang, S.Q.[Shi-Qiang],
A Framework for Heuristic Scheduling for Parallel Processing on Multicore Architecture: A Case Study With Multiview Video Coding,
CirSysVideo(19), No. 11, November 2009, pp. 1658-1666.
IEEE DOI 0912
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Seitner, F.H., Bleyer, M., Gelautz, M., Beuschel, R.M.,
Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding,
CirSysVideo(19), No. 11, November 2009, pp. 1667-1679.
IEEE DOI 0912
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Hubert, H., Stabernack, B.,
Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures,
CirSysVideo(19), No. 11, November 2009, pp. 1680-1691.
IEEE DOI 0912
BibRef

Rhu, M.S.[Min-Soo], Park, I.C.[In-Cheol],
Optimization of Arithmetic Coding for JPEG2000,
CirSysVideo(20), No. 3, March 2010, pp. 446-451.
IEEE DOI 1003
BibRef
Earlier:
Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000,
ICIP09(2665-2668).
IEEE DOI 0911
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And:
Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding,
ICIP09(2673-2676).
IEEE DOI 0911
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Gurler, C.G.[C. Goktug], Aksay, A.[Anil], Akar, G.B.[Gozde Bozdagi], Tekalp, A.M.[A. Murat],
Architectures for multi-threaded MVC-compliant multi-view video decoding and benchmark tests,
SP:IC(25), No. 5, June 2010, pp. 325-334.
Elsevier DOI 1007
MVC; Decoding; Multi-threaded; Multi-core; Real-time BibRef

Li, Y.R.[Yi-Ran], Liu, Y.[Yang], Zhang, T.[Tong],
Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators,
SP:IC(25), No. 5, June 2010, pp. 335-344.
Elsevier DOI 1007
Motion estimation (ME); 3D memory stacking BibRef

Dikbas, S.[Salih], Zhai, F.[Fan],
Lossless image compression using adjustable fractional line-buffer,
SP:IC(25), No. 5, June 2010, pp. 345-351.
Elsevier DOI 1007
Lossless compression; Low-complexity; Embedded systems; SoC BibRef

Jung, J.[Jongpil], Kim, J.[Jaemoon], Kyung, C.M.[Chong-Min],
A Dynamic Search Range Algorithm for Stabilized Reduction of Memory Traffic in Video Encoder,
CirSysVideo(20), No. 7, July 2010, pp. 1041-1046.
IEEE DOI 1008
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Tsai, T.H.[Tsung-Han], Lee, Y.H.[Yu-Hsuan],
A 6.4 Gbit/s Embedded Compression Codec for Memory-Efficient Applications on Advanced-HD Specification,
CirSysVideo(20), No. 10, October 2010, pp. 1277-1291.
IEEE DOI 1011
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Schuchter, A.[Arthur], Uhl, A.[Andreas],
Embedded hardware low cost JPEG 2000 video coding system: Hardware coder for surveillance type videos,
RealTimeIP(5), No. 3, September 2010, pp. 149-162.
WWW Link. 1011
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Schuchter, A.[Arthur], Uhl, A.[Andreas],
Fast motion estimation approaches for surveillance type videos in an inter-frame JPEG 2000-based adaptive video coding system,
IET-IPR(6), No. 1, 2012, pp. 31-42.
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Li, G.L.[Gwo-Long], Chang, T.S.[Tian-Sheuan],
RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access,
CirSysVideo(20), No. 11, November 2010, pp. 1565-1576.
IEEE DOI 1011
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Li, G.L.[Gwo-Long], Chang, T.S.[Tian-Sheuan],
An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension,
CirSysVideo(23), No. 11, 2013, pp. 1837-1848.
IEEE DOI 1312
CMOS integrated circuits BibRef

Chang, I.J., Mohapatra, D., Roy, K.,
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications,
CirSysVideo(21), No. 2, February 2011, pp. 101-112.
IEEE DOI 1103
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Wen, X., Au, O.C., Xu, J., Fang, L., Cha, R., Li, J.,
Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture,
CirSysVideo(21), No. 2, February 2011, pp. 206-219.
IEEE DOI 1103
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Gupte, A.D., Amrutur, B., Mehendale, M.M., Rao, A.V., Budagavi, M.,
Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding,
CirSysVideo(21), No. 2, February 2011, pp. 225-230.
IEEE DOI 1103
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Thevennin, M.[Mathieu], Paindavoine, M.[Michel], Letellier, L.[Laurent], Schmit, R.[Renaud], Heyrman, B.[Barthelemy],
The eISP low-power and tiny silicon footprint programmable video architecture,
RealTimeIP(6), No. 1, March 2011, pp. 33-46.
WWW Link. 1103
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Gorin, J.[Jérôme], Wipliez, M.[Matthieu], Prêteux, F.[Françoise], Raulet, M.[Mickaël],
LLVM-based and scalable MPEG-RVC decoder,
RealTimeIP(6), No. 1, March 2011, pp. 59-70.
WWW Link. 1103
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Tsai, T.H., Fang, T.L., Pan, Y.N.,
A Novel Design of CAVLC Decoder With Low Power and High Throughput Considerations,
CirSysVideo(21), No. 3, March 2011, pp. 311-319.
IEEE DOI 1104
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Chen, X., Zhao, Z., Rahmati, A., Wang, Y., Zhong, L.,
Sensor-Assisted Video Encoding for Mobile Devices in Real-World Environments,
CirSysVideo(21), No. 3, March 2011, pp. 335-349.
IEEE DOI 1104
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Wong, C.W.[Chau-Wai], Siu, W.C.[Wan-Chi],
Analysis of Dyadic Approximation Error for Hybrid Video Codecs With Integer Transforms,
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IEEE DOI 1110
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Wong, C.W.[Chau-Wai], Siu, W.C.[Wan-Chi],
Transform Kernel Selection Strategy for the H.264/AVC and Future Video Coding Standards,
CirSysVideo(21), No. 11, November 2011, pp. 1631-1645.
IEEE DOI 1111
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Chen, O.T.C., Hsia, M.L.[Meng-Lin], Chen, C.C.[Chih-Chang],
Low-Complexity Inverse Transforms of Video Codecs in an Embedded Programmable Platform,
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IEEE DOI 1110
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Kim, H.[Haksoo], Kim, M.B.[Man-Bae],
A Selective Protection Scheme for Scalable Video Coding,
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IEEE DOI 1111
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Earlier:
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PSIVT06(732-741).
Springer DOI 0612
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Caviedes, J.E.,
The Evolution of Video Processing Technology and Its Main Drivers,
PIEEE(100), No. 4, April 2012, pp. 872-877.
IEEE DOI 1204
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Li, Y., Zhang, T.,
Reducing DRAM Image Data Access Energy Consumption in Video Processing,
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IEEE DOI 1204
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Zhao, B., Zhang, X., Chen, S., Low, K.S., Zhuang, H.,
A 64X64 CMOS Image Sensor With On-Chip Moving Object Detection and Localization,
CirSysVideo(22), No. 4, April 2012, pp. 581-588.
IEEE DOI 1204
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Licciardo, G.D., Albanese, L.F.,
Design of a context-adaptive variable length encoder for real-time video compression on reconfigurable platforms,
IET-IPR(6), No. 4, 2012, pp. 301-308.
DOI Link 1205
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Chen, J.W.[Jian-Wen], Zheng, J.H.[Jian-Hua], Xu, F.[Feng], Villasenor, J.D.,
Adaptive Frequency Weighting for High-Performance Video Coding,
CirSysVideo(22), No. 7, July 2012, pp. 1027-1036.
IEEE DOI 1208
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Chao, Y.C., Kao, C.H., Liu, B.D., Yang, J.F.,
Efficient inverse transform architectures for multi-standard video coding applications,
IET-IPR(6), No. 6, 2012, pp. 647-660.
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Correa, G.[Guilherme], Assuncao, P.A.[Pedro A.], Agostini, L.V.[Luciano V.], da Silva Cruz, L.A.[Luis A.],
Performance and Computational Complexity Assessment of High-Efficiency Video Encoders,
CirSysVideo(22), No. 12, December 2012, pp. 1899-1909.
IEEE DOI 1302
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Kim, S.D.[Sung Dae], Sunwoo, M.H.[Myung Hoon],
MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor,
CirSysVideo(23), No. 10, 2013, pp. 1767-1780.
IEEE DOI 1311
CMOS integrated circuits BibRef

Ren, R.[Rong], Wei, J.G.[Jian-Guo], Juarez, E.[Eduardo], Garrido, M.[Matias], Sanz, C.[Cesar], Pescador, F.[Fernando],
A PMC-driven methodology for energy estimation in RVC-CAL video codec specifications,
SP:IC(28), No. 10, 2013, pp. 1303-1314.
Elsevier DOI 1312
RVC-CAL BibRef

Yviquel, H.[Hervé], Boutellier, J.[Jani], Raulet, M.[Mickaël], Casseau, E.[Emmanuel],
Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs,
SP:IC(28), No. 10, 2013, pp. 1295-1302.
Elsevier DOI 1312
Co-design BibRef

Dhoot, C., Chau, L.P.[Lap-Pui], Chowdhury, S.R., Mooney, V.J.,
Low Power Motion Estimation Based on Probabilistic Computing,
CirSysVideo(24), No. 1, January 2014, pp. 1-14.
IEEE DOI 1402
CMOS integrated circuits BibRef

Elhamzi, W.[Wajdi], Dubois, J.[Julien], Miteran, J.[Johel], Atri, M.[Mohamed],
An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding,
RealTimeIP(9), No. 1, March 2014, pp. 19-30.
Springer DOI 1403
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Lee, B.[Bumshik], Kim, M.C.[Mun-Churl], Kim, H.Y.[Hui Yong], Choi, J.S.[Jin Soo],
Performance analysis of hierarchical transform coding with a large kernel for video codecs,
IET-PR(8), No. 1, January 2014, pp. 12-22.
DOI Link 1403
correlation methods BibRef

Li, H., Wang, Y., Li, P.,
A Time-Frequency Hybrid Downmixing Method for AC-3 Decoding,
SPLetters(21), No. 8, August 2014, pp. 933-936.
IEEE DOI 1406
Decoding BibRef

Senapati, R.K., Pati, U.C., Mahapatra, K.K.,
Reduced memory, low complexity embedded image compression algorithm using hierarchical listless discrete tchebichef transform,
IET-IPR(8), No. 4, April 2014, pp. 213-238.
DOI Link 1407
data compression BibRef

Xu, W.Z.[Wei-Zhi], Yu, H.[Hui], Lu, D.J.[Dian-Jie], Song, F.L.[Feng-Long], Wang, D.[Da], Ye, X.C.[Xiao-Chun], Pei, S.W.[Song-Wei], Fan, D.R.[Dong-Rui], Xie, H.T.[Hong-Tao],
Fast and scalable lock methods for video coding on many-core architecture,
JVCIR(25), No. 7, 2014, pp. 1758-1762.
Elsevier DOI 1410
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And: Corrigendum: JVCIR(26), No. 1, 2015, pp. 350-.
Elsevier DOI 1502
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And: Corrigendum: JVCIR(27), No. 1, 2015, pp. 57-.
Elsevier DOI 1502
Many-core BibRef

Oliveira, P.A.M., Cintra, R.J., Bayer, F.M., Kulasekera, S., Madanayake, A.,
A Discrete Tchebichef Transform Approximation for Image and Video Coding,
SPLetters(22), No. 8, August 2015, pp. 1137-1141.
IEEE DOI 1502
approximation theory BibRef

Li, M.S.[Mian-Shiuan], Chen, M.J.[Mei-Juan], Yeh, C.H.[Chia-Hung], Tai, K.H.[Kuang-Han],
Performance improvement of multi-view video coding based on geometric prediction and human visual system,
IJIST(25), No. 1, 2015, pp. 41-49.
DOI Link 1502
multi-view video coding BibRef

Tsai, C., Chen, Y., Tseng, C.,
An Efficient Application Processor Architecture for Multicore Software Video Decoding,
CirSysVideo(25), No. 2, February 2015, pp. 325-338.
IEEE DOI 1502
Decoding BibRef

Guo, L.[Li], Zhou, D.J.[Da-Jiang], Goto, S.,
A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec,
MultMed(16), No. 8, December 2014, pp. 2323-2332.
IEEE DOI 1502
VLSI BibRef

Wang, Z.Y.[Zhen-Yu], Dong, S.F.[Sheng-Fu], Wang, R.G.[Rong-Gang], Wang, W.M.[Wen-Min], Gao, W.[Wen],
Dynamic macroblock wavefront parallelism for parallel video coding,
JVCIR(28), No. 1, 2015, pp. 36-43.
Elsevier DOI 1503
Video encoding BibRef

Hwang, Y., Lyu, M., Lin, C.,
A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video,
CirSysVideo(25), No. 4, April 2015, pp. 674-687.
IEEE DOI 1504
Bit rate BibRef

Blasi, S.G., Mrak, M., Izquierdo, E.,
Frequency-Domain Intra Prediction Analysis and Processing for High-Quality Video Coding,
CirSysVideo(25), No. 5, May 2015, pp. 798-811.
IEEE DOI 1505
Decoding BibRef

Mrak, M.[Marta], Gabriellini, A.[Andrea], Flynn, D.[David], Davies, T.[Thomas],
Parallel processing for combined intra prediction in high efficiency video coding,
ICIP11(3489-3492).
IEEE DOI 1201
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Liu, L.[Leibo], Wang, D.[Dong], Zhu, M.[Min], Wang, Y.S.[Yan-Sheng], Yin, S.Y.[Shou-Yi], Cao, P.[Peng], Yang, J.[Jun], Wei, S.J.[Shao-Jun],
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding,
MultMed(17), No. 10, October 2015, pp. 1706-1720.
IEEE DOI 1511
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And: Correction: MultMed(17), No. 12, December 2015, pp. 2354-2355.
IEEE DOI 1512
energy conservation. Arrays BibRef

Lian, X., Liu, Z., Zhou, W., Duan, Z.,
Lossless Frame Memory Compression Using Pixel-Grain Prediction and Dynamic Order Entropy Coding,
CirSysVideo(26), No. 1, January 2016, pp. 223-235.
IEEE DOI 1601
Encoding BibRef

Yin, H.B.[Hai-Bing], Park, D.S.[Dong Sun], Zhang, X.Y.[Xiao Yun],
Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation,
RealTimeIP(11), No. 3, March 2016, pp. 507-525.
WWW Link. 1604
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Jambek, A.B.[Asral Bahari], Juri, A.A.[Arief Affendi],
Low-energy motion estimation architecture using quadrant-based multi-octagon (QBMO) algorithm,
RealTimeIP(12), No. 3, October 2016, pp. 623-632.
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Kulkarni, M.V.[Milind V.], Kulkarni, D.B.,
Analysis of fractal inter frame video coding using parallel approach,
SIViP(11), No. 4, May 2017, pp. 629-634.
Springer DOI 1704
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Oliveira, P.A.M., Cintra, R.J., Bayer, F.M., Kulasekera, S., Madanayake, A.,
Low-Complexity Image and Video Coding Based on an Approximate Discrete Tchebichef Transform,
CirSysVideo(27), No. 5, May 2017, pp. 1066-1076.
IEEE DOI 1705
Approximation algorithms, Approximation methods, Complexity theory, Discrete cosine transforms, Image coding, Video coding, Approximate transforms, discrete Tchebichef transform (DTT), fast algorithms, image, and, video, coding BibRef


Bian, J., Lin, W.Y., Matsushita, Y., Yeung, S.K., Nguyen, T.D., Cheng, M.M.,
GMS: Grid-Based Motion Statistics for Fast, Ultra-Robust Feature Correspondence,
CVPR17(2828-2837)
IEEE DOI 1711
Coherence, Real-time systems, Robustness, Silicon, Standards BibRef

Rao, T., Ikenaga, T.,
Quadrant segmentation and ring-like searching based FPGA implementation of ORB matching system for Full-HD video,
MVA17(89-92)
DOI Link 1708
Clocks, Databases, Detectors, Feature extraction, Hardware, Image segmentation, Table lookup BibRef

Santos, L., Gómez, A., Hernández-Fernández, P., Sarmiento, R.,
SystemC modelling of lossless compression IP cores for space applications,
DASIP16(65-72)
IEEE DOI 1704
IP networks BibRef

Paim, G., Goebel, J., Penny, W., Zatt, B., Porto, M., Agostini, L.,
High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards,
ICIP16(2162-2166)
IEEE DOI 1610
Hardware BibRef

Paim, G., Penny, W., Goebel, J., Afonso, V., Susin, A., Porto, M., Zatt, B., Agostini, L.,
An efficient sub-sample interpolator hardware for VP9-10 standards,
ICIP16(2167-2171)
IEEE DOI 1610
Indexes BibRef

Eilertsen, G., Mantiuk, R.K., Unger, J.,
A high dynamic range video codec optimized by large-scale testing,
ICIP16(1379-1383)
IEEE DOI 1610
Bit rate BibRef

Saxena, A.[Ankur], Aabed, M.[Mohammed], Budagavi, M.[Madhukar],
Low-complexity separable multiplier-less loop filter for video coding,
ICIP15(3715-3719)
IEEE DOI 1512
ALF BibRef

Momcilovic, S.[Svetislav], Ilic, A.[Aleksandar], Roma, N.[Nuno], Sousa, L.[Leonel],
Collaborative inter-prediction on CPU-GPU systems,
ICIP14(1228-1232)
IEEE DOI 1502
Collaboration BibRef

Yin, H.B.[Hai-Bing], Li, S.H.[Shiz-Hong], Hu, H.Q.[Hong-Qi],
Multiple target performance evaluation model for HD video encoder VLSI architecture design,
VCIP13(1-4)
IEEE DOI 1402
VLSI BibRef

Zhao, L.[Lili], Xu, J.Z.[Ji-Zheng], Zhou, Y.[You], Ai, M.J.[Ming-Jing],
A dynamic slice control scheme for slice-parallel video encoding,
ICIP12(713-716).
IEEE DOI 1302
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Belyaev, E.[Evgeny], Turlikov, A.[Andrey], Egiazarian, K.[Karen], Gabbouj, M.[Moncef],
An efficient multiplication-free and look-up table-free adaptive binary arithmetic coder,
ICIP12(701-704).
IEEE DOI 1302
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Sezer, O.G.[Osman G.], Demircin, M.U.[Mehmet U.], Zhou, M.[Minhua],
A DSP-based solution to increase the energy efficiency of real-time video encoders,
ICIP12(2921-2924).
IEEE DOI 1302
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Chen, Z.F.[Zhi-Feng], Reznik, Y.[Yuriy],
Analysis of video codec buffer and delay under time-varying channel,
VCIP12(1-6).
IEEE DOI 1302
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Elhamzi, W.[Wajdi], Dubois, J.[Julien], Miteran, J.[Johel], Atri, M.[Mohamed], Tourki, R.[Rached],
Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances,
ACIVS12(96-107).
Springer DOI 1209
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Tsai, C.S.[Chun-Shian], Chen, H.L.[Hsuan-Liang],
The Implementation of Multimedia Decoder Framework for Android on PAC Duo Platform,
DICTA11(382-387).
IEEE DOI 1205
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Li, T.[Tao], Liu, Z.T.[Zhen-Tao],
Video Stream Processing on a High Performance Reconfigurable Architecture,
DICTA11(388-393).
IEEE DOI 1205
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Ma, Z.[Zhan], Segall, A.[Andrew],
Frame buffer compression for low-power video coding,
ICIP11(757-760).
IEEE DOI 1201
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Ma, T.[Tao], Shrestha, P.[Pradhumna], Hempel, M.[Michael], Peng, D.M.[Dong-Ming], Sharif, H.[Hamid],
Low-complexity image coder/decoder with an approaching-entropy quad-tree search code for embedded computing platforms,
ICIP11(297-300).
IEEE DOI 1201
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Dondi, P.[Piercarlo], Lombardi, L.[Luca], Cinque, L.[Luigi],
RDVideo: A New Lossless Video Codec on GPU,
CIAP11(II: 158-167).
Springer DOI 1109
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Tonomura, Y.[Yoshihide], Nakachi, T.[Takayuki], Shirai, D.[Daisuke], Fujii, T.[Tatsuya], Kiya, H.[Hitoshi],
Color-component bit allocation scheme for JPEG 2000 parallel codec,
ICIP10(1345-1348).
IEEE DOI 1009
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Song, J.H.[Joon-Ho], Kim, D.H.[Doo Hyun], Kim, D.H.[Do-Hyung], Lee, S.H.[Shi Hwa],
High-performance memory interface architecture for high-definition video coding application,
ICIP10(3745-3748).
IEEE DOI 1009
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Ismail, Y.[Yasser], McNeely, J.[Jason], Shaaban, M.[Mohsen], Al Najjar, M.[Mayssaa], Bayoumi, M.A.[Magdy A.],
A fast discrete transform architecture for Frequency Domain Motion Estimation,
ICIP10(1249-1252).
IEEE DOI 1009
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Ismail, Y.[Yasser], Shaaban, M.[Mohsen], McNeely, J.[Jason], Bayoumi, M.A.[Magdy A.],
An efficient adaptive manipulation architecture for real time video coding in Frequency Domain,
ICIP09(3281-3284).
IEEE DOI 0911
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Pang, Y.[Yi], Wen, J.T.[Jiang-Tao], Sun, L.[Lifeng], Hu, W.D.[Wei-Dong], Yang, S.Q.[Shi-Qiang],
Frame-level heuristic scheduling Multi-view Video Coding on symmetric multi-core architecture,
ICIP09(2305-2308).
IEEE DOI 0911
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Song, B.C.[Byung Cheol], Yi, Y.[Yongseok], Lee, Y.G.[Yun-Gu], Ko, J.H.[Jun Hyuk], Kim, T.H.[Tae Hee],
1080P 60HZ intra-frame CODEC based on RGB color space for wireless AV streaming,
ICIP09(2657-2660).
IEEE DOI 0911
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Yao, C.L.[Chun-Lian], Li, W.[Wei], Gao, L.H.[Li-Hua], Chen, Y.[Yi],
Extended Video Encoder with Pre-Processing of Interlace Signal,
CISP09(1-4).
IEEE DOI 0910
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Pan, R.[Rong], Liu, Y.[Yu],
An Evaluation Method for View Random Access of Multiview Video Coding,
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Yamamoto, H.[Hiroshi], Hyodo, K.[Katsuya], Wakamiya, N.[Naoki], Murata, M.[Masayuki],
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Lu, X., Manduchi, R.,
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Tripathi, S.[Shikha], Vikas, R., Jain, R.C.,
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Molino, A., Vacca, F., Masera, G.,
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Dubois, J., Mattavelli, M., Pierrefeu, L., Miteran, J.,
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López, M.F., Rodríguez, S.G., Ortiz, J.P.G., Dana, J.M., Ruiz, V.G., García, I.,
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Ishwar, P., Ramchandran, K.,
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Liu, T.M.[Tsu-Ming], Lee, C.Y.[Chen-Yi],
A low-complexity soft VLC decoder using performance modeling,
ICIP04(V: 3233-3236).
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Xie, G.[Gui], Shen, H.[Hong],
A highly scalable speck image coder,
ICIP04(II: 1297-1300).
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Lu, L.G.[Li-Gang], Sheinin, V.,
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ICIP04(V: 2861-2864).
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Hill, R., Fung, J., Mann, S.,
A parallel mediated reality platform,
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Marpe, D.M., Wiegand, T.,
A highly efficient multiplication-free binary arithmetic coder and its application in video coding,
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Chou, C.H.[Chun-Hsien], Liu, K.C.[Kuo-Cheng], Lin, P.Y.[Po-Yu],
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Hibrid-SoC: a multi-core architecture for image and video applications,
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Sachs, D.G., Adve, S.V., Jones, D.L.,
Cross-layer adaptive video coding to reduce energy on general-purpose processors,
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Liu, L.C.[Li-Chang], Chien, J.C.[Jong-Chih], Chuang, H.Y.H., Li, C.C.,
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ICIP02(I: 872-875).
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Ali, W., van Zon, K.,
Optimizing a Random System of Cascaded Video Processing Modules by Parallel Evolution Modeling,
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Tsang, P.W.M.[Peter Wai Ming], Lee, W.T.,
A novel interpolative codec for low bit rate applications,
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Zhang, K.[Kui], Kittler, J.V.,
Using background memory for efficient video coding,
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Zhang, K.[Kui], Bober, M., Kittler, J.V.,
A hybrid codec for very low bit rate video coding,
ICIP96(I: 641-644).
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Nguyen, T., Zakhor, A., Yelick, K.,
Performance Analysis of an H.263 Video Encoder for Viram,
ICIP00(Vol III: 98-101).
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Lin, W., Tye, B., Ong, E., Xiong, C., Miki, T.[Toshio], Hotani, S.[Sanae],
Systematic Analysis and Methodology of Real-time DSP Implementation for Hybrid Video Coding,
ICIP99(III:847-851).
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Chen, C.H.[Cheng-Hsien], Lee, C.Y.[Chen-Yi],
A Cost-Effective Lighting Processor for 3D Graphics Application,
ICIP99(II:792-796).
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Chen, J., and Liu, K.,
A Fully Pipelined Parallel CORDIC Architecture for Half-pel Motion Estimation,
ICIP97(II: 574-577).
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Cheng, S.C., and Hang, H.M.,
The Impact of Rate Control Algorithms on Video Codec Hardware Design,
ICIP97(II: 807-810).
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Bergmann, N., and Chung, Y.,
Video Compression on FPGA-Based Custom Computers,
ICIP97(I: 361-364).
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Mattavelli, M., Brunetton, S., and Mlynek, D.,
Computational Graceful Degradation for Video Sequence Decoding,
ICIP97(I: 330-333).
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Ng, K.T., Chan, S.C., Ng, T.S.,
Buffer control algorithm for low bit-rate video compression,
ICIP96(I: 685-688).
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High performance VLSI architecture for the trellis coded quantization,
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Brahmbhatt, A.,
A VLSI architecture for real time code book generator and encoder of a vector quantizer,
ICIP96(II: 991-994).
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Ruedi, P.F., Marchal, P.R., Arreguit, X.,
A mixed digital-analog SIMD chip tailored for image perception,
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Legat, J.D., Cornil, J.P., Macq, D., Verleysen, M.,
A real-time VLSI-based architecture for multi-motion estimation,
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Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
H.264 Coding, Decoding: Hardware and Systems .


Last update:Nov 18, 2017 at 20:56:18