5.4.13 Hardware and Architecture for Coding

Chapter Contents (Back)
Hardware. Architectures. Image Compression. Primarily single image coding issues. See also Motion and Video Coding: Hardware and Systems.

Wang, C.L.[Chin-Liang], Chen, C.Y.[Chang-Yu],
High-throughput VLSI architectures for the 1-D and 2-D discrete cosine transforms,
CirSysVideo(5), No. 1, February 1995, pp. 31-40.
IEEE Top Reference. 0206
BibRef

Hsia, S.C.[Shih-Chang], Liu, B.D.[Bin-Da], Yang, J.F.[Jar-Ferr], Bai, B.L.[Bor-Long],
VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor,
CirSysVideo(5), No. 5, October 1995, pp. 396-406.
IEEE Top Reference. 0206
BibRef

Venbrux, J., Yeh, P.S., Liu, M.N.,
A VLSI chip set for high-speed lossless data compression,
CirSysVideo(2), No. 4, December 1992, pp. 381-391.
IEEE Top Reference. 0206
BibRef

Balram, N., Moura, J.M.F.,
Noncausal Predictive Image Codec,
IP(5), No. 8, August 1996, pp. 1229-1242.
IEEE DOI 9608
BibRef

Bull, D.R., Redmill, D.W.,
Optimization of Image-Coding Algorithms and Architectures Using Genetic Algorithms,
IndEle(43), No. 5, October 1996, pp. 549-558. 9610
BibRef

Redmill, D.W.[David W.], Bull, D.R.,
Non-linear perfect reconstruction filter banks for image coding,
ICIP96(I: 593-596).
IEEE DOI BibRef 9600

Redmill, D.W.[David W.], Bull, D.R.,
Error Resilient Arithmetic Coding of Still Images,
ICIP96(II: 109-112).
IEEE DOI BibRef 9600

Redmill, D.W., Kingsbury, N.G.,
Still image coding for noisy channels,
ICIP94(I: 95-99).
IEEE DOI 9411
BibRef

Ancona, F., Rovetta, S., Zunino, R.,
An Efficient Technique for Implementing an Image Compression Neural Algorithm on Concurrent Multiprocessor,
EngAAI(10), No. 6, December 1997, pp. 573-580. 9807
BibRef

Masselos, K., Stouraitis, T., Goutis, C.E.,
Novel scheme for low-power classified vector quantisation image coding,
VISP(145), No. 6, December 1998, pp. 408. BibRef 9812

Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.,
A Novel Algorithm for Low Power Image and Video Coding,
CirSysVideo(8), No. 3, June 1998, pp. 258-263.
IEEE Top Reference. 9806
BibRef

Acken, K.P., Irwin, M.J., Owens, R.M.,
A Parallel ASIC Architecture for Efficient Fractal Image-Coding,
VLSIVideo(19), No. 2, July 1998, pp. 97-113. 9809
BibRef

Kim, S., Sung, W.,
Fixed-Point Error Analysis and Word Length Optimization of 8 x 8 IDCT Architectures,
CirSysVideo(8), No. 8, December 1998, pp. 935.
IEEE Top Reference. BibRef 9812

Bi, M., Ong, S.H., Ang, Y.H.,
Integer-Modulated FIR Filter Banks for Image Compression,
CirSysVideo(8), No. 8, December 1998, pp. 923.
IEEE Top Reference. BibRef 9812

Jiang, J.M.[Jian-Min],
A novel parallel design of a codec for black and white image compression,
SP:IC(8), No. 5, July 1996, pp. 465-474.
WWW Link. BibRef 9607

Lim, H.G., Pang, K.K., Tan, T.K., Hall, S.C.,
A low complexity H.261-compatible software video decoder,
SP:IC(8), No. 1, January 1996, pp. 25-37.
WWW Link. BibRef 9601

Baskurt, A., Odet, C., Goutte, R.,
Image coding on the Phobos space probe,
SP:IC(6), No. 5, October 1994, pp. 479-484.
WWW Link. BibRef 9410

Chang, W.W., Wang, D.Y.,
Quality enhancement of sinusoidal transform vocoders,
VISP(145), No. 6, December 1998, pp. 379. BibRef 9812

Pang, T.C.J., Choy, C.S.O., Chan, C.F., Cham, W.K.,
A Self-Timed ICT Chip for Image Coding,
CirSysVideo(9), No. 6, September 1999, pp. 856. BibRef 9909

Kassim, A.A., Chua, K.S., Fong, F.K., Ranganath, S.,
DSP-based system for real-time video communications,
IJIST(10), No. 1, 1999, pp. 47-53. BibRef 9900

Zhao, D., Chan, Y.K., Gao, W.[Wen],
Low-complexity and low-memory entropy coder for image compression,
CirSysVideo(11), No. 10, October 2001, pp. 1140-1145.
IEEE Top Reference. 0110
BibRef

Tzou, K.H.,
High-order entropy coding for images,
CirSysVideo(2), No. 1, March 1992, pp. 87-89.
IEEE Top Reference. 0206
BibRef

Lei, S.M., Sun, M.T., Tzou, K.H.,
Design and hardware architecture of high-order conditional entropy coding for images,
CirSysVideo(2), No. 2, June 1992, pp. 176-186.
IEEE Top Reference. 0206
BibRef

Wei, B.W.Y., Meng, T.H.,
A parallel decoder of programmable Huffman codes,
CirSysVideo(5), No. 2, April 1995, pp. 175-178.
IEEE Top Reference. 0206
BibRef
Earlier:
A programmable parallel Huffman decoder,
ICIP94(III: 668-671).
IEEE DOI 9411
BibRef

Wan, X.[Xia], Wang, Y.L.[Yi-Liang], Chen, W.H.,
Dynamic range analysis for the implementation of fast transform,
CirSysVideo(5), No. 2, April 1995, pp. 178-180.
IEEE Top Reference. 0206
BibRef

Ravasi, M., Tenze, L., Mattavelli, M.,
A scalable and programmable architecture for 2-d DWT decoding,
CirSysVideo(12), No. 8, August 2002, pp. 671-677.
IEEE Top Reference. 0208
BibRef

Mitchell, J.L.[Joan L.], Cazes, A.N.[Albert N.], Leeder, N.M.[Neil M.],
Fast JPEG huffman encoding and decoding,
US_Patent6,373,412, Apr 16, 2002
WWW Link. BibRef 0204

Wang, C.N., Yang, S.W., Liu, C.M., Chiang, T.,
A Hierarchical N-Queen Decimation Lattice and Hardware Architecture for Motion Estimation,
CirSysVideo(14), No. 4, April 2004, pp. 429-440.
IEEE Abstract. 0407
BibRef

Pastuszak, G.[Grzegorz],
A High-Performance Architecture for Embedded Block Coding in JPEG 2000,
CirSysVideo(15), No. 9, September 2005, pp. 1182-1191.
IEEE DOI 0509
BibRef
Earlier:
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder,
CIAP05(604-611).
Springer DOI 0509
BibRef

Pastuszak, G.[Grzegorz],
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC,
CirSysVideo(18), No. 7, July 2008, pp. 949-960.
IEEE DOI 0808
BibRef

Corsonello, P., Perri, S., Staino, G., Lanuzza, M., Cocorullo, G.,
Low Bit Rate Image Compression Core for Onboard Space Applications,
CirSysVideo(16), No. 1, January 2006, pp. 114-128.
IEEE DOI 0601
BibRef

Gupta, A.K., Nooshabadi, S., Taubman, D., Dyer, M.,
Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000,
CirSysVideo(16), No. 7, July 2006, pp. 843-858.
IEEE DOI 0608
BibRef

Dyer, M.[Michael], Nooshabadi, S.[Saeid], Taubman, D.[David],
Design and Analysis of System on a Chip Encoder for JPEG2000,
CirSysVideo(19), No. 2, February 2009, pp. 215-225.
IEEE DOI 0902
BibRef
Earlier:
Analysis of Multiple Parallel Block Coding in JPEG2000,
ICIP07(V: 173-176).
IEEE DOI 0709
BibRef

Li, Y., Bayoumi, M.,
A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000,
CirSysVideo(16), No. 9, September 2006, pp. 1153-1163.
IEEE DOI 0610
BibRef

van Dyck, W.[Walter], Smodic, R.[Rene], Hufnagl, H.[Herbert], Berndorfer, T.[Thomas],
High-speed JPEG coder implementation for a smart camera,
RealTimeIP(1), No. 1, October 2006, pp. 63-68.
Springer DOI 0001
BibRef

Zhang, Y.Z.[Yi-Zhen], Xu, C.[Chao], Wang, W.T., Chen, L.B.,
Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000,
CirSysVideo(17), No. 10, October 2007, pp. 1336-1347.
IEEE DOI 0711
BibRef

Zhang, Y.Z.[Yi-Zhen], Xu, C.[Chao],
Analysis and Effective Parallel Technique for Rate-Distortion Optimization in JPEG2000,
ICIP06(2465-2468).
IEEE DOI 0610
BibRef
Earlier:
Analysis and High Performance Parallel Architecture Design for EBCOT in JPEG2000,
ICIP05(III: 996-999).
IEEE DOI 0512
BibRef

Kurdthongmee, W.,
A novel Kohonen SOM-based image compression architecture suitable for moderate density FPGAs,
IVC(26), No. 8, 1 August 2008, pp. 1094-1105.
WWW Link. 0806
Image quantization; Image compression; FPGA-based implementation; Kohonen self-organizing map BibRef

Kurdthongmee, W.,
Utilization of a rational-based representation to improve the image quality of a hardware-based K-SOM quantizer,
RealTimeIP(6), No. 3, September 2011, pp. 199-211.
WWW Link. 1108
BibRef

Kurdthongmee, W.,
A hardware centric algorithm for the best matching unit searching stage of the SOM-based quantizer and its FPGA implementation,
RealTimeIP(12), No. 1, June 2016, pp. 71-80.
WWW Link. 1606
BibRef

Balasingham, I.[Ilangko], Ramstad, T.A.[Tor A.],
Are the Wavelet Transforms the Best Filter Banks for Image Compression?,
JIVP(2008), No. 2008, pp. xx-yy.
DOI Link 0804
BibRef
Earlier:
Optimized Perfect Reconstruction Tree-Structured Filter Banks for Image Coding,
ICIP96(I: 585-588).
IEEE DOI BibRef

Papadonikolakis, M.E.[Markos E.], Kakarountas, A.P.[Athanasios P.], Goutis, C.E.[Costas E.],
Efficient high-performance implementation of JPEG-LS encoder,
RealTimeIP(3), No. 4, December 2008, pp. xx-yy.
Springer DOI 0811
BibRef

Sarawadekar, K.[Kishor], Banerjee, S.[Swapna],
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000,
CirSysVideo(21), No. 6, June 2011, pp. 825-836.
IEEE DOI 1101
BibRef
Earlier:
Efficient VLSI architecture for bit plane encoder of JPEG 2000,
ICIP09(2805-2808).
IEEE DOI 0911
BibRef

Kim, H.S., Lee, J., Kim, H., Kang, S., Park, W.C.,
A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC,
CirSysVideo(21), No. 11, November 2011, pp. 1581-1587.
IEEE DOI 1111
BibRef

Lei, S.F., Lo, C.C., Kuo, C.C., Shieh, M.D.,
Low-power context-based adaptive binary arithmetic encoder using an embedded cache,
IET-IPR(6), No. 4, 2012, pp. 309-317.
DOI Link 1205
BibRef

Lo, C.C., Hsu, C.W., Shieh, M.D.,
Low-complexity multi-standard variable length coding decoder using tree-based partition and classification,
IET-PR(7), No. 3, 2013, pp. -.
DOI Link 1307
BibRef

Huang, K.K.[Ke-Kun], Dai, D.Q.[Dao-Qing],
A New On-Board Image Codec Based on Binary Tree With Adaptive Scanning Order in Scan-Based Mode,
GeoRS(50), No. 10, October 2012, pp. 3737-3750.
IEEE DOI 1210
BibRef

Tseng, C.F., Lai, Y.T.,
Hardware-software co-design architecture for joint photo expert graphic XR encoder,
IET-IPR(6), No. 9, 2012, pp. 1284-1292.
DOI Link 1302
Comments: See also Comments on and corrections to Hardware: software co-design architecture for joint photo expert graphic XR encoder. BibRef

He, K., Gerstlauer, A., Orshansky, M.,
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems,
CirSysVideo(23), No. 6, 2013, pp. 961-974.
IEEE DOI 1307
Discrete cosine transforms BibRef

Lucking, D.J.[David J.], Balster, E.J.[Eric J.], Hill, K.L.[Kerry L.], Scarpino, F.A.[Frank A.],
FPGA implementation of the JPEG2000 binary arithmetic (MQ) decoder,
RealTimeIP(8), No. 4, December 2013, pp. 411-419.
Springer DOI 1312
BibRef

Saidani, T.[Taoufik], Atri, M.[Mohamed], Khriji, L.[Lazhar], Tourki, R.[Rached],
An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000,
RealTimeIP(11), No. 1, January 2016, pp. 63-74.
Springer DOI 1601
BibRef

Shi, C., Zhang, J., Zhang, Y.,
A Novel Vision-Based Adaptive Scanning for the Compression of Remote Sensing Images,
GeoRS(54), No. 3, March 2016, pp. 1336-1348.
IEEE DOI 1603
Discrete wavelet transforms BibRef

Do, T.T.T., Nguyen, B.P.,
Comments on and corrections to 'Hardware: software co-design architecture for joint photo expert graphic XR encoder',
IET-IPR(10), No. 9, 2016, pp. 681-682.
DOI Link 1609
hardware-software codesign See also Hardware-software co-design architecture for joint photo expert graphic XR encoder. BibRef

Bartrina-Rapesta, J., Blanes, I., Aulí-Llinās, F., Serra-Sagristā, J., Sanchez, V., Marcellin, M.W.,
A Lightweight Contextual Arithmetic Coder for On-Board Remote Sensing Data Compression,
GeoRS(55), No. 8, August 2017, pp. 4825-4835.
IEEE DOI 1708
Context, Context modeling, Data compression, Encoding, Entropy, Image coding, Remote sensing, Arithmetic coding, Consultative Committee for Space Data Systems (CCSDS)-123, lossless and near-lossless coding, remote, sensing, data, compression BibRef


Gmira, F., Hraoui, S., Saaidi, A., Oulidi, A.J., Satori, K.,
Securing the architecture of the JPEG compression by an dynamic encryption,
ISCV15(1-6)
IEEE DOI 1506
cryptography BibRef

Cao, H.H.[Hai-Heng], Zhang, Y.F.[Yong-Fei], Jiang, H.X.[Hong-Xu],
A high-throughput MQ coder architecture based on dependence extraction method,
ICIP14(1203-1207)
IEEE DOI 1502
Entropy coder in JPEG2000. BibRef

Mcnichols, J.M.[John M.], Balster, E.J.[Eric J.], Turri, W.F.[William F.], Hill, K.L.[Kerry L.],
Implementation and Analysis of Jpeg2000 System on a Chip,
ISVC12(II: 545-556).
Springer DOI 1209
BibRef

Sameen, I., Chang, Y.C.[Yoong Choon], Ng, M.S.[Mow Song], Goi, B.M.[Bok-Min], Lee, C.S.[Chee Siong],
High-Level Synthesis of a Unified 2-D DWT System Architecture for JPEG2000 Using FPGAs,
PSIVT10(226-231).
IEEE DOI 1011
BibRef

Lucking, D.[David], Balster, E.J.[Eric J.],
An Increased Throughput FPGA Design of the JPEG2000 Binary Arithmetic Decoder,
DICTA10(400-405).
IEEE DOI 1012
BibRef

Liu, K.[Kai], Li, Y.S.[Yun-Song],
A dual symbol arithmetic coder architecture with reduced memory for JPEG2000,
ICIP10(513-516).
IEEE DOI 1009
BibRef

Maalouf, A.[Aldo], Larabi, M.C.[Mohamed-Chaker],
Low-complexity enhanced lapped transform for image coding in JPEG XR / HD photo,
ICIP09(5-8).
IEEE DOI 0911
BibRef

Wang, X.[Xiao], Cao, B.Y.[Bai-Yang],
Design of 8-Bit Serial Real-Time Decoder Based on Complex Programmable Logic Device,
CISP09(1-3).
IEEE DOI 0910
BibRef

Hu, H.P.[Hong-Ping], Zhao, Z.Y.[Zhong-Yuan],
A Real-Time High Resolution Image Compression System Based on ADV212,
CISP09(1-4).
IEEE DOI 0910
BibRef

Zhang, Z.[Zhe], Cao, P.[Peng], Chen, H.[Hu],
A New Hardware and Software Co-Design of JPEG2000 Encoder,
CISP09(1-4).
IEEE DOI 0910
BibRef

Chatterjee, S.K., Chakrabarti, I.,
Algorithm and architecture for quarter pixel motion estimation for H.264/AVC,
NCVPRIPG13(1-4)
IEEE DOI 1408
VLSI BibRef

Suman, T.[Tenugu], Chatterjee, S.K.[Sumit Kumar], Chakrabarti, I.[Indrajit],
High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000,
ICCVGIP08(232-237).
IEEE DOI 0812
BibRef

Tsai, C.F.[Cheng-Fa], Lin, Y.J.[Yu-Jiun],
LazySOM: Image Compression Using an Enhanced Self-Organizing Map,
PSIVT09(118-129).
Springer DOI 0901
BibRef

Chien, C.Y.[Ching-Yen], Huang, S.C.[Sheng-Chieh], Lin, S.H.[Shih-Hsiang], Huang, Y.C.[Yu-Chieh], Chen, Y.C.[Yi-Cheng], Chou, L.C.[Lei-Chun], Chuang, T.D.[Tzu-Der], Chang, Y.W.[Yu-Wei], Pan, C.H.[Chia-Ho], Chen, L.G.[Liang-Gee],
A 100 MHz 1920X1080 HD-Photo 20 frames/sec JPEG XR encoder design,
ICIP08(1384-1387).
IEEE DOI 0810
BibRef

Lisani, J.L., Rudin, L., Monasse, P., Morel, J.M., Yu, P.,
Meaningful automatic video demultiplexing with unknown number of cameras, contrast changes, and motion,
AVSBS05(604-608).
IEEE DOI 0602
BibRef

Ruiz, G.A., Michell, J.A., Buron, A.M.,
High Throughput 2D DCT/IDCT Processor for Video Coding,
ICIP05(III: 1036-1039).
IEEE DOI 0512
BibRef

Chou, C.H.[Chun-Hsien], Liu, K.C.[Kuo-Cheng], Lin, C.S.[Chien-Sheng],
Perceptually Optimized JPEG2000 Coder Based on CIEDE2000 Color Difference Equation,
ICIP05(III: 1184-1187).
IEEE DOI 0512
See also Perceptually Tuned Watermarking Scheme for Color Images, A. BibRef

Li, J.[Jin],
The seamlessly multiplexed embedded codec (SMEC) and its application in image coding,
ICIP04(II: 1285-1288).
IEEE DOI 0505
BibRef

Belbachir, A.N., Hofstatter, M., Milosevic, N., Schon, P.,
Embedded contours extraction for high-speed scene dynamics based on a neuromorphic temporal contrast vision sensor,
EmbedCV08(1-8).
IEEE DOI 0806
BibRef

Reimers, C., Belbachir, A.N., Bischof, H., Ottensamer, R., Cesarsky, D.A., Feuchtgruber, H., Kerschbaum, F., Poglitsch, A.,
A feasibility study of on-board data compression for infrared cameras of space observatories,
ICPR04(I: 524-527).
IEEE DOI 0409
BibRef

Lee, K., Chang, H., Chun, S., Choi, H., Sull, S.,
Perception-based Image Transcoding for Universal Multimedia Access,
ICIP01(II: 475-478).
IEEE DOI 0108
BibRef

Mateu, P., Prades, J.,
Sequential Logic Compression of Images,
ICIP01(II: 479-482).
IEEE DOI 0108
BibRef

Liang, S., Lee, J.S.,
Design and Modeling of the Generally Adopted Progressive Image Transmission Regulator and Its Application,
ICIP01(I: 90-93).
IEEE DOI 0108
BibRef

Kuroki, Y., Ueshige, Y., Ohta, T.,
An Estimation of the Predictors Implemented by Shift Operation, Addition, and/or Subtraction,
ICIP01(III: 474-477).
IEEE DOI 0108
BibRef

Hsieh, J.,
Transpose Memory for Video Rate JPEG Compression on Highly Parallel Single-chip Digital Cmos Imager,
ICIP00(Vol III: 102-105).
IEEE DOI 0008
BibRef

Hanjalic, A.[Alan], Lagendijk, R.L.[Reginald L.], Biemond, J.[Jan],
Efficient image CODEC with reduced content access work,
ICIP99(III:807-811).
IEEE DOI BibRef 9900

Grattarola, A., Iscra, A., Zappatore, S.,
A simple multi-layer digital video coder for multimedia network applications,
CIAP99(992-996).
IEEE DOI 9909
BibRef

Hamamoto, T., Ohtsuka, Y., Aizawa, K.,
New Design and Implementation of On-sensor-compression,
MVA98(xx-yy). BibRef 9800
And:
128X128 pixels image sensor for on-sensor-compression,
ICIP98(I: 493-497).
IEEE DOI 9810
BibRef

Aizawa, K., Hamamoto, T., Otsuka, Y., Hatori, M., and Abe, M.,
Implementations of on Sensor Image Compression and Comparisons Between Pixel and Column Parallel Architectures,
ICIP97(II: 258-261).
IEEE DOI BibRef 9700

Aizawa, K., Hamamoto, T., Egi, Y., Hatori, M., Yamazaki, J.,
On sensor image compression for high pixel rate imaging: pixel parallel and column parallel architectures,
ICIP96(II: 1019-1022).
IEEE DOI 9610
BibRef

Tan, W., Chang, E., Zakhor, A.[Avideh],
Real time software implementation of scalable video codec,
ICIP96(I: 17-20).
IEEE DOI BibRef 9600

Nicolas, H., Jordan, F.[Frederic],
Interactive-optimization and massively parallel implementations of video compression algorithms,
ICIP96(I: 229-232).
IEEE DOI BibRef 9600

Molloy, S., Schoner, B., Madisetti, A., Jain, R., Matic, R.,
An algorithm-driven processor design for video compression,
ICIP94(III: 611-615).
IEEE DOI 9411
BibRef

Aizawa, K., Ohno, H., Hamamoto, T., Hatori, M., Yamazaki, J.,
A novel image sensor for video compression,
ICIP94(III: 591-595).
IEEE DOI 9411
BibRef

Albanesi, M.G., Ferretti, M., Leoni, S.,
A hierarchical compression engine,
ICPR94(C:391-394).
IEEE DOI 9410
BibRef

Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
Multi Dimensional Coding, Stereo Coding, Disparity Maps, 3-D Shapes .


Last update:Nov 11, 2017 at 13:31:57