5.5.12.2 HEVC Coding, Decoding: Hardware and Systems

Hautala, I., Boutellier, J., Hannuksela, J., Silven, O.,
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering,
CirSysVideo(25), No. 7, July 2015, pp. 1217-1230.
IEEE DOI 1507
Decoding BibRef

Abeydeera, M., Karunaratne, M., Karunaratne, G., de Silva, K., Pasqual, A.,
4K Real-Time HEVC Decoder on an FPGA,
CirSysVideo(26), No. 1, January 2016, pp. 236-249.
IEEE DOI 1601
Computer architecture BibRef

Zhou, W.[Wei], Zhang, J.Z.[Jing-Zhi], Zhou, X.[Xin], Liu, Z.Y.[Zhen-Yu], Liu, X.X.[Xiao-Xiang],
A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter,
MultMed(18), No. 6, June 2016, pp. 1034-1047.
IEEE DOI 1605
Encoding BibRef

Zhou, W.[Wei], Zhang, J.Z.[Jing-Zhi], Zhou, X.[Xin], Liu, T.Q.[Tong-Qing],
A high-throughput deblocking filter VLSI architecture for HEVC,
VCIP15(1-4)
IEEE DOI 1605
Algorithm design and analysis BibRef

Wei, H., Zhou, W., Zhou, X., Duan, Z.,
An efficient all zero block detection algorithm based on frequency characteristics of DCT in HEVC,
VCIP15(1-4)
IEEE DOI 1605
Algorithm design and analysis BibRef

Pastuszak, G.,
Hardware architectures for the H.265/HEVC discrete cosine transform,
IET-IPR(9), No. 6, 2015, pp. 468-477.
DOI Link 1507
discrete cosine transforms BibRef

Pastuszak, G.,
Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization,
CirSysVideo(25), No. 11, November 2015, pp. 1844-1856.
IEEE DOI 1511
Clocks BibRef

Pastuszak, G., Abramowski, A.,
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder,
CirSysVideo(26), No. 1, January 2016, pp. 210-222.
IEEE DOI 1601
Algorithm design and analysis BibRef

Chiang, P.T., Ting, Y.C., Chen, H.K., Jou, S.Y., Chen, I.W., Fang, H.C., Chang, T.S.,
A QFHD 30-frames/s HEVC Decoder Design,
CirSysVideo(26), No. 4, April 2016, pp. 724-735.
IEEE DOI 1604
Bandwidth BibRef

He, J.[Jing], Yang, F.Z.[Fu-Zheng],
High-speed implementation of rate-distortion optimized quantization for H.264/AVC,
SIViP(9), No. 3, March 2015, pp. 543-551.
WWW Link. 1503
BibRef

He, J.[Jing], Yang, F.Z.[Fu-Zheng], Zhou, Y.,
High-speed implementation of rate-distortion optimised quantisation for H.265/HEVC,
IET-IPR(9), No. 8, 2015, pp. 652-661.
DOI Link 1506
quantisation (signal) BibRef

He, J.[Jing], Yang, F.Z.[Fu-Zheng],
Efficient frame-level bit allocation algorithm for H.265/HEVC,
IET-IPR(11), No. 4, April 2017, pp. 245-257.
DOI Link 1704
BibRef

Correa, G.[Guilherme], Assuncao, P.A.[Pedro A.], Agostini, L.V.[Luciano V.], da Silva Cruz, L.A.[Luis A.],
Complexity scalability for real-time HEVC encoders,
RealTimeIP(12), No. 1, June 2016, pp. 107-122.
Springer DOI 1606
BibRef
Earlier:
Four-step algorithm for early termination in HEVC inter-frame prediction based on decision trees,
VCIP14(65-68)
IEEE DOI 1504
computational complexity BibRef

Corrêa, G.[Guilherme], Assunção, P.A.[Pedro A.], Agostini, L.V.[Luciano V.], da Silva Cruz, L.A.[Luis A.],
Pareto-Based Method for High Efficiency Video Coding With Limited Encoding Time,
CirSysVideo(26), No. 9, September 2016, pp. 1734-1745.
IEEE DOI 1609
Business process re-engineering BibRef

da Silva, T.L., Agostini, L.V., da Silva Cruz, L.A.,
Complexity reduction of depth intra coding for 3D video extension of HEVC,
VCIP14(229-232)
IEEE DOI 1504
computational complexity BibRef

Jin, X.[Xin], Dai, Q.H.[Qiong-Hai],
Clustering-Based Content Adaptive Tiles Under On-chip Memory Constraints,
MultMed(18), No. 12, December 2016, pp. 2331-2344.
IEEE DOI 1612
Complexity theory HEVC BibRef

Wang, S., Zhou, D., Zhou, J., Yoshimura, T., Goto, S.,
VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications,
CirSysVideo(27), No. 2, February 2017, pp. 380-393.
IEEE DOI 1702
Bandwidth BibRef

Grellert, M.[Mateus], Zatt, B.[Bruno], Shafique, M.[Muhammad], Bampi, S.[Sergio], Henkel, J.[Jörg],
Complexity control of HEVC encoders targeting real-time constraints,
RealTimeIP(13), No. 1, March 2017, pp. 5-24.
Springer DOI 1704
BibRef

Rodríguez-Sánchez, R.[Rafael], Quintana-Ortí, E.S.[Enrique S.],
Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors,
RealTimeIP(13), No. 1, March 2017, pp. 25-38.
WWW Link. 1704
BibRef

Saldanha, M.[Mário], Sanchez, G.[Gustavo], Zatt, B.[Bruno], Porto, M.[Marcelo], Agostini, L.[Luciano],
Energy-aware scheme for the 3D-HEVC depth maps prediction,
RealTimeIP(13), No. 1, March 2017, pp. 55-69.
WWW Link. 1704
BibRef

Sanchez, G.[Gustavo], Marcon, C.[César], Agostini, L.[Luciano],
Real-time scalable hardware architecture for 3D-HEVC bipartition modes,
RealTimeIP(13), No. 1, March 2017, pp. 71-83.
WWW Link. 1704
BibRef

Zhang, Y.H.[Yu-Hua], Wang, Y.[Yong], Zhu, C.[Ce], Lin, Y.B.[Yong-Bing], Zheng, J.H.[Jian-Hua],
Optimization of depth modeling modes in 3D-HEVC depth intra coding,
RealTimeIP(13), No. 1, March 2017, pp. 85-100.
WWW Link. 1704
Get Access BibRef

Hsu, P.K., Shen, C.A.,
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems,
CirSysVideo(27), No. 5, May 2017, pp. 1091-1103.
IEEE DOI 1705
Complexity theory, Encoding, Filtering, Memory management, Throughput, Very large scale integration, Deblocking filter (DBF), High Efficiency Video Coding (HEVC), VLSI, memory BibRef

Liu, L.B.[Lei-Bo], Chen, Y.J.[Ying-Jie], Deng, C.C.[Chen-Chen], Yin, S.[Shouyi], Wei, S.J.[Shao-Jun],
Implementation of in-loop filter for HEVC decoder on reconfigurable processor,
IET-IPR(11), No. 9, September 2017, pp. 685-692.
DOI Link 1709
BibRef

Khemiri, R.[Randa], Kibeya, H.[Hassan], Sayadi, F.E.[Fatma Ezahra], Bahri, N.[Nejmeddine], Atri, M.[Mohamed], Masmoudi, N.[Nouri],
Optimisation of HEVC motion estimation exploiting SAD and SSD GPU-based implementation,
IET-IPR(12), No. 2, February 2018, pp. 243-253.
DOI Link 1801
BibRef

Zhou, J., Zhou, D., Zhang, S., Kimura, S., Goto, S.,
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC,
CirSysVideo(28), No. 2, February 2018, pp. 556-560.
IEEE DOI 1802
Clocks, Context, Decoding, Delays, Encoding, Table lookup, Throughput, Arithmetic decoder, H.265, High Efficiency Video Coding (HEVC), context adaptive binary arithmetic coding (CABAC) BibRef

Wang, B.[Biao], de Souza, D.F.[Diego Felix], Alvarez-Mesa, M.[Mauricio], Chi, C.C.[Chi Ching], Juurlink, B.[Ben], Ilic, A.[Aleksandar], Roma, N.[Nuno], Sousa, L.[Leonel],
Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU,
SP:IC(62), 2018, pp. 93-105.
Elsevier DOI 1802
BibRef

Kim, H., Ko, J., Park, S.,
An Efficient Architecture of In-Loop Filters for Multicore Scalable HEVC Hardware Decoders,
MultMed(20), No. 4, April 2018, pp. 810-824.
IEEE DOI 1804
Decoding, Encoding, Hardware, Information filtering, Multicore processing, Throughput, HEVC, Multicore, architecture, sample adaptive offset (SAO) BibRef

Katayama, T.[Takafumi], Song, T.[Tian], Shi, W.[Wen], Jiang, X.T.[Xian-Tao], Shimamoto, T.[Takashi],
Boundary correlation-based intracoding for SHVC algorithm and its efficient VLSI architecture,
RealTimeIP(15), No. 1, June 2018, pp. 107-122.
Springer DOI 1806
BibRef

Fan, Y., Huang, L., Hao, B., Zeng, X.,
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation,
CirSysVideo(28), No. 8, August 2018, pp. 2048-2057.
IEEE DOI 1808
Hardware, Encoding, Algorithm design and analysis, Diamond, Software, Motion estimation, 2-D data reuse, coding performance, SAD tree BibRef

Cui, J., Xiong, R., Zhang, X., Wang, S., Wang, S., Ma, S., Gao, W.,
Hybrid All Zero Soft Quantized Block Detection for HEVC,
IP(27), No. 10, October 2018, pp. 4987-5001.
IEEE DOI 1808
discrete cosine transforms, quantisation (signal), rate distortion theory, video coding, HEVC, rate-distortion modeling BibRef

Wang, H.L.[Han-Li], Xiao, B.[Bo], Wu, J.[Jun], Kwong, S.[Sam], Kuo, C.C.J.[C.C. Jay],
A Collaborative Scheduling-Based Parallel Solution for HEVC Encoding on Multicore Platforms,
MultMed(20), No. 11, November 2018, pp. 2935-2948.
IEEE DOI 1810
Encoding, Parallel processing, Multicore processing, Image coding, Video coding, Instruction sets, High efficiency video coding, parallelization scalability BibRef

Xiao, B.[Bo], Wang, H.L.[Han-Li], Wu, J.[Jun], Kwong, S.[Sam], Kuo, C.C.J.[C.C. Jay],
A Multi-Grained Parallel Solution for HEVC Encoding on Heterogeneous Platforms,
MultMed(21), No. 12, December 2019, pp. 2997-3009.
IEEE DOI 1912
Graphics processing units, Encoding, Parallel processing, Central Processing Unit, Image coding, Video coding, heterogeneous computing BibRef

Vayalil, N.C., Paul, M., Kong, Y.,
A Residue Number System Hardware Design of Fast-Search Variable-Motion-Estimation Accelerator for HEVC/H.265,
CirSysVideo(29), No. 2, February 2019, pp. 572-581.
IEEE DOI 1902
Hardware, Encoding, Motion estimation, Prediction algorithms, Video coding, Software algorithms, Software, very large scale integration (VLSI) architecture BibRef

Jiang, H., Fan, R., Zhang, Y., Wang, G., Li, Z.,
Highly Paralleled Low-Cost Embedded HEVC Video Encoder on TI KeyStone Multicore DSP,
CirSysVideo(29), No. 4, April 2019, pp. 1163-1178.
IEEE DOI 1904
Encoding, Data communication, Multicore processing, Real-time systems, Streaming media, Hardware, Decoding, HEVC, embedded system BibRef

Alcocer, E.[Estefania], Gutierrez, R.[Roberto], Lopez-Granado, O.[Otoniel], Malumbres, M.P.[Manuel P.],
Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder,
RealTimeIP(16), No. 2, April 2019, pp. 547-557.
Springer DOI 1904
BibRef

Zhang, Y., Lu, C.,
A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder,
CirSysVideo(29), No. 5, May 2019, pp. 1544-1558.
IEEE DOI 1905
Estimation, Hardware, Bit rate, Encoding, Syntactics, Distortion, intra encoder BibRef

Grellert, M., Zatt, B., Bampi, S., da Silva Cruz, L.A.,
Fast Coding Unit Partition Decision for HEVC Using Support Vector Machines,
CirSysVideo(29), No. 6, June 2019, pp. 1741-1753.
IEEE DOI 1906
Encoding, Support vector machines, Complexity theory, Training, Rate-distortion, Bit rate, Machine learning, Fast mode decision, HEVC BibRef

Sampaio, F.M., Zatt, B., Shafique, M., Henkel, J., Bampi, S.,
Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC,
CirSysVideo(29), No. 10, October 2019, pp. 3046-3060.
IEEE DOI 1910
data compression, energy conservation, energy consumption, memory architecture, SRAM chips, storage management, video codecs, adaptivity BibRef

Monteiro, E.[Eduarda], Grellert, M.[Mateus], Zatt, B.[Bruno], Bampi, S.[Sergio],
Energy-aware cache hierarchy assessment targeting HEVC encoder execution,
RealTimeIP(16), No. 5, October 2019, pp. 1695-1715.
Springer DOI 1911
BibRef

Ahn, Y.J.[Yong-Jo], Yoo, J.[Jonghun], Jo, H.H.[Hyun-Ho], Sim, D.G.[Dong-Gyu],
Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders,
RealTimeIP(16), No. 6, December 2019, pp. 2173-2187.
WWW Link. 1912
BibRef

Liao, T.T.[Tzu-Ting], Shen, C.A.[Chung-An], Tseng, Y.H.[Yu-Hao],
The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems,
RealTimeIP(16), No. 6, December 2019, pp. 1943-1958.
WWW Link. 1912
BibRef

Jia, L., Tsui, C., Au, O.C., Jia, K.,
A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation,
CirSysVideo(30), No. 1, January 2020, pp. 243-255.
IEEE DOI 2002
computational complexity, high definition video, motion estimation, systolic arrays, video coding, HEVC, computation reuse BibRef

Hu, Q.A.[Qi-Ang], Zhou, J.[Jun], Zhang, X.Y.[Xiao-Yun], Gao, Z.Y.[Zhi-Yong], Sun, M.T.[Ming-Ting],
In-loop perceptual model-based rate-distortion optimization for HEVC real-time encoder,
RealTimeIP(17), No. 2, April 2020, pp. 293-311.
Springer DOI 2004
BibRef

Jridi, M.[Maher], Alfalou, A.[Ayman], Meher, P.K.[Pramod K.],
Efficient approximate core transform and its reconfigurable architectures for HEVC,
RealTimeIP(17), No. 2, April 2020, pp. 329-339.
WWW Link. 2004
BibRef

Shi, L.Z.[Long-Zhao], Gao, X.O.[Xia-Ohong], Yang, X.Z.[Xiu-Zhi], Chen, Z.F.[Zhi-Feng], Zheng, M.K.[Ming-Kui],
Algorithm optimization and hardware implementation for Merge mode in HEVC,
RealTimeIP(17), No. 3, June 2020, pp. 623-630.
Springer DOI 2006
BibRef

Du, G.M.[Gao-Ming], Cao, Y.F.[Yi-Fan], Li, Z.M.[Zhen-Min], Zhang, D.L.[Duo-Li], Wang, L.[Li], Song, Y.K.[Yu-Kun], Ouyang, Y.M.[Yi-Ming],
A low-latency DMM-1 encoder for 3D-HEVC,
RealTimeIP(17), No. 3, June 2020, pp. 691-702.
Springer DOI 2006
BibRef

Xiao, W., He, H., Wang, T., Chao, H.,
The Interpretable Fast Multi-Scale Deep Decoder for the Standard HEVC Bitstreams,
MultMed(22), No. 7, July 2020, pp. 1680-1691.
IEEE DOI 2007
Videos, Encoding, Decoding, Standards, Redundancy, Computational efficiency, Neural networks, HEVC, interpretability BibRef

Li, T., Xu, M., Deng, X., Shen, L.,
Accelerate CTU Partition to Real Time for HEVC Encoding With Complexity Control,
IP(29), 2020, pp. 7482-7496.
IEEE DOI 2007
High efficiency video coding, coding tree unit partition, complexity control BibRef

Tariq, J.[Junaid],
High-performance intra-mode accelerator for HEVC,
VC(36), No. 8, August 2020, pp. 1603-1617.
WWW Link. 2007
BibRef

Chatterjee, S., Sarawadekar, K.,
Exploiting Trigonometric Properties to Optimize Higher Order DCT Architecture in HEVC,
CirSysVideo(30), No. 10, October 2020, pp. 3598-3607.
IEEE DOI 2010
Discrete cosine transforms, Matrix decomposition, Hardware, Complexity theory, Video compression, DCT, ASIC BibRef

Paim, G., Rocha, L.M.G., Amrouch, H., da Costa, E.A.C., Bampi, S., Henkel, J.,
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders,
CirSysVideo(30), No. 10, October 2020, pp. 3814-3828.
IEEE DOI 2010
Adders, Encoding, Video coding, Logic gates, Mathematical model, Power dissipation, Approximate computing, SAD BibRef

Shi, L.Z.[Long-Zhao], Zhang, Z.Y.[Zhi-Yong], Luo, L.[Long], Yang, X.Z.[Xiu-Zhi], Chen, Z.F.[Zhi-Feng], Yang, X.L.[Xiao-Ling], Fu, C.[Chen],
Parallel spiral search algorithm applied to integer motion estimation,
SP:IC(95), 2021, pp. 116279.
Elsevier DOI 2106
Parallel spiral search, HEVC, Inter prediction, Hardware-friendly motion estimation BibRef

Menasri, W.[Wahiba], Djabri, M.[Manel], Chennoufi, S.[Sarah], Skoudarli, A.[Abdellah], Bouhedda, M.[Mounir], Benzineb, O.[Omar],
Hardware implementation of HEVC CABAC binarization/de-binarization,
JVCIR(89), 2022, pp. 103673.
Elsevier DOI 2212
Binarization, CABAC, De-binarization, FPGA, HEVC, Matlab, VHDL BibRef

Su, L.[LiChao], Cao, M.Q.[Meng-Qing], Yu, Y.[Yue], Chen, J.[Jian], Yang, X.[XiuZhi], Wu, D.P.[Da-Peng],
Dynamic convolutional capsule network for In-loop filtering in HEVC video codec,
IET-IPR(17), No. 2, 2023, pp. 439-449.
DOI Link 2302
BibRef

Brai, R.[Radhia.], Bekhouch, A.[Amara], Doghmane, N.[Noureddine], Harize, S.[Saliha], Kouadria, N.[Nasreddine],
Low calculation cost of HEVC coding unit size based on spatial homogeneity detection,
JVCIR(93), 2023, pp. 103819.
Elsevier DOI 2305
CU size decision, Complexity reduction, Spatial homogeneity BibRef

Zhang, Y.[Yuan], Gong, X.L.[Xiao-Li], Yu, H.L.[Hua-Long], Wu, Z.J.[Zi-Jun], Yu, L.[Lu],
Distance-based feature repack algorithm for video coding for machines,
JVCIR(102), 2024, pp. 104150.
Elsevier DOI 2407
Collaborative intelligence, Deep feature compression, H.265/HEVC, Action recognition, Video coding for machines BibRef

Nguyen Huu, T., van Duong, V., Jeon, B.,
Random-access-aware Light Field Video Coding using Tree Pruning Method,
VCIP20(128-131)
IEEE DOI 2102
Complexity theory, Encoding, Decoding, Video coding, Light fields, Image coding, Correlation, Light Field video, compression, MV-HEVC, random-access BibRef

Willème, A., Macq, B., Descampe, A., Rouvroy, G.,
Power-Aware HEVC Compression Through Asymmetric JPEG XS Frame Buffer Compression,
ICIP18(3598-3602)
IEEE DOI 1809
Bandwidth, System-on-chip, Transform coding, Encoding, Decoding, Streaming media, Memory management, HEVC, JPEG XS, hardware, embedded compression BibRef

Papadopoulos, P.K., Koziri, M., Loukopoulos, T.,
A Fast Heuristic for Tile Partitioning and Processor Assignment in HEVC,
ICIP18(4143-4147)
IEEE DOI 1809
Encoding, Partitioning algorithms, Load management, Task analysis, Processor scheduling, Instruction sets, Video recording, Tiles, HEVC BibRef

Tang, J., Huang, Y., Xie, R., Luo, Z., Song, L.,
GPU Based Motion-Compensated Frame Interpolation Acceleration for Future Video Coding,
ICIP18(306-310)
IEEE DOI 1809
Graphics processing units, Interpolation, Acceleration, Kernel, Encoding, Instruction sets, FVC, Frame Interpolation, GPU BibRef

Mallik, B., Akbari, A.S., Kor, A.L.,
Mixed-resolution HEVC based multiview video codec,
3DTV-CON17(1-4)
IEEE DOI 1804
data compression, image resolution, image sequences, video coding, MV-HEVC codec, asymmetric spatial interview video codecs, video compression BibRef

Deng, Z., Moccagatta, I.,
Hardware-friendly inter prediction techniques for AV1 video coding,
ICIP17(948-952)
IEEE DOI 1803
Computational modeling, Context modeling, Decoding, Encoding, Hardware, Pipelines, Tools, AV1, VP9, hardware implementation, reference motion vector BibRef

Hojati, E., Franche, J.F., Coulombe, S., Vázquez, C.,
Highly parallel HEVC motion estimation based on multiple temporal predictors and nested diamond search,
ICIP17(2746-2750)
IEEE DOI 1803
Artificial intelligence, GPU, HEVC, massively parallel architecture, rate-constrained motion estimation BibRef

Kufa, J., Kratochvil, T.,
Software and hardware HEVC encoding,
WSSIP17(1-5)
IEEE DOI 1707
Central Processing Unit, Encoding, Graphics processing units, High definition video, Image coding, HEVC, HM, NVENC, Turing encoder, x265 BibRef

Parois, R., Hamidouche, W., Mora, E.G., Raulet, M., Deforges, O.,
Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder,
DASIP16(11-17)
IEEE DOI 1704
parallel architectures BibRef

Gomez, A.[Augusto], Perea, J.[Jhon], Trujillo, M.[Maria],
Parallel Integer Motion Estimation for High Efficiency Video Coding (HEVC) Using OpenCL,
CIARP16(68-75).
Springer DOI 1703
BibRef

Gu, J., Han, Y., Wen, J.,
A novel low delay in-loop filtering WPP process for parallel HEVC encoding,
VCIP16(1-4)
IEEE DOI 1701
Delays BibRef

Takano, F., Igarashi, H., Moriyoshi, T.,
4K-UHD real-time HEVC encoder with GPU accelerated motion estimation,
ICIP17(2731-2735)
IEEE DOI 1803
BibRef
Earlier: A2, A1, A3:
Highly parallel transformation and quantization for HEVC encoder on GPUs,
VCIP16(1-4)
IEEE DOI 1701
Acceleration, Computational complexity, Encoding, Graphics processing units, Indexes, Motion estimation, Parallel Processing BibRef

Kalali, E., Hamzaoglu, I.,
FPGA implementations of HEVC Inverse DCT using high-level synthesis,
DASIP15(1-6)
IEEE DOI 1605
discrete cosine transforms BibRef

Stabernack, B., Möller, J., Hahlbeck, J., Brandenburg, J.,
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support,
DASIP15(1-2)
IEEE DOI 1605
field programmable gate arrays BibRef

Baik, H.K.[Hyun-Ki], Song, H.J.[Hwang-Jun],
A complexity-based adaptive tile partitioning algorithm for HEVC decoder parallelization,
ICIP15(4298-4302)
IEEE DOI 1512
HEVC; Parallel Processing; Tile; Video coding BibRef

Abeydeera, M.[Maleen], Pasqual, A.[Ajith],
HEVC inverse transform architecture utilizing coefficient sparsity,
ICIP15(4848-4852)
IEEE DOI 1512
BibRef

Yu, Q.[Quanhe], Zheng, X.Z.[Xiao-Zhen], Zheng, J.H.[Jian-Hua], He, Y.[Yun], Yu, W.[Wei], Wang, D.D.[Da-Dong], Chen, J.Y.[Jun-You], Xu, Y.Y.[Yang-Yang],
High-throughput and low-complexity binary arithmetic decoder based on logarithmic domain,
ICIP15(3305-3309)
IEEE DOI 1512
Arithmetic coding; CABAC; H.265/HEVC; LBAC; entropy coding BibRef

Maich, H.[Henrique], Paim, G.[Guilherme], Afonso, V.[Vladimir], Agostini, L.[Luciano], Zatt, B.[Bruno], Porto, M.[Marcelo],
A multi-standard interpolation hardware solution for H.264 and HEVC,
ICIP15(2910-2914)
IEEE DOI 1512
Fractional Motion Estimation; H.264; HEVC; Hardware Design BibRef

Bariani, M.[Massimo], Lambruschini, P.[Paolo], Raggio, M.[Marco], Pezzoni, L.[Luca],
An Efficient SIMD Implementation of the H.265 Decoder for Mobile Architecture,
QoEM15(563-570).
Springer DOI 1511
BibRef

Chen, G., Pei, Z., Liu, Z., Ikenaga, T.,
Deblocking strength prediction based CTU-level SAO category determination in HEVC encoder,
VCIP15(1-4)
IEEE DOI 1605
Bit rate BibRef

Jiang, Y.B.[Yue-Bing], Llamocca, D., Pattichis, M., Esakki, G.,
A unified and pipelined hardware architecture for implementing intra prediction in HEVC,
Southwest14(29-32)
IEEE DOI 1406
indexing BibRef

Karwowski, D.[Damian],
Improved Adaptive Arithmetic Coding for HEVC Video Compression Technology,
ICCVG12(121-128).
Springer DOI 1210
BibRef

Karwowski, D.[Damian], Domanski, M.[Marek],
Improved Context-Based Adaptive Binary Arithmetic Coding in MPEG-4 AVC/H.264 Video Codec,
ICCVG10(II: 25-32).
Springer DOI 1009
BibRef

Li, F.[Fu], Shi, G.M.[Guang-Ming], Wu, F.[Feng],
An efficient VLSI architecture for 4X4 intra prediction in the High Efficiency Video Coding (HEVC) standard,
ICIP11(373-376).
IEEE DOI 1201
BibRef

Sinangil, M.E.[Mahmut E.], Chandrakasan, A.P.[Anantha P.], Sze, V.[Vivienne], Zhou, M.H.[Min-Hua],
Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard,
ICIP12(1529-1532).
IEEE DOI 1302
BibRef

Sinangil, M.E.[Mahmut E.], Chandrakasan, A.P.[Anantha P.], Sze, V.[Vivienne], Zhou, M.H.[Min-Hua],
Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine,
ICIP12(1533-1536).
IEEE DOI 1302
BibRef

Sze, V.[Vivienne], Chandrakasan, A.P.[Anantha P.], Budagavi, M.[Madhukar], Zhou, M.H.[Min-Hua],
Parallel CABAC for low power video coding,
ICIP08(2096-2099).
IEEE DOI 0810
BibRef

Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
Single Chip, Chipset for Coding .