5.5.10.2 HEVC Coding, Decoding: Hardware and Systems

Chapter Contents (Back)
Hardware. HEVC Hardware. VLSI.

Hautala, I., Boutellier, J., Hannuksela, J., Silven, O.,
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering,
CirSysVideo(25), No. 7, July 2015, pp. 1217-1230.
IEEE DOI 1507
Decoding BibRef

Abeydeera, M., Karunaratne, M., Karunaratne, G., De Silva, K., Pasqual, A.,
4K Real-Time HEVC Decoder on an FPGA,
CirSysVideo(26), No. 1, January 2016, pp. 236-249.
IEEE DOI 1601
Computer architecture BibRef

Zhou, W.[Wei], Zhang, J.Z.[Jing-Zhi], Zhou, X.[Xin], Liu, Z.Y.[Zhen-Yu], Liu, X.X.[Xiao-Xiang],
A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter,
MultMed(18), No. 6, June 2016, pp. 1034-1047.
IEEE DOI 1605
Encoding BibRef

Zhou, W.[Wei], Zhang, J.Z.[Jing-Zhi], Zhou, X.[Xin], Liu, T.Q.[Tong-Qing],
A high-throughput deblocking filter VLSI architecture for HEVC,
VCIP15(1-4)
IEEE DOI 1605
Algorithm design and analysis BibRef

Wei, H., Zhou, W., Zhou, X., Duan, Z.,
An efficient all zero block detection algorithm based on frequency characteristics of DCT in HEVC,
VCIP15(1-4)
IEEE DOI 1605
Algorithm design and analysis BibRef

Pastuszak, G.,
Hardware architectures for the H.265/HEVC discrete cosine transform,
IET-IPR(9), No. 6, 2015, pp. 468-477.
DOI Link 1507
discrete cosine transforms BibRef

Pastuszak, G.,
Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization,
CirSysVideo(25), No. 11, November 2015, pp. 1844-1856.
IEEE DOI 1511
Clocks BibRef

Pastuszak, G., Abramowski, A.,
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder,
CirSysVideo(26), No. 1, January 2016, pp. 210-222.
IEEE DOI 1601
Algorithm design and analysis BibRef

Chiang, P.T., Ting, Y.C., Chen, H.K., Jou, S.Y., Chen, I.W., Fang, H.C., Chang, T.S.,
A QFHD 30-frames/s HEVC Decoder Design,
CirSysVideo(26), No. 4, April 2016, pp. 724-735.
IEEE DOI 1604
Bandwidth BibRef

He, J.[Jing], Yang, F.[Fuzheng],
High-speed implementation of rate-distortion optimized quantization for H.264/AVC,
SIViP(9), No. 3, March 2015, pp. 543-551.
WWW Link. 1503
BibRef

He, J.[Jing], Yang, F.[Fuzheng], Zhou, Y.,
High-speed implementation of rate-distortion optimised quantisation for H.265/HEVC,
IET-IPR(9), No. 8, 2015, pp. 652-661.
DOI Link 1506
quantisation (signal) BibRef

He, J.[Jing], Yang, F.[Fuzheng],
Efficient frame-level bit allocation algorithm for H.265/HEVC,
IET-IPR(11), No. 4, April 2017, pp. 245-257.
DOI Link 1704
BibRef

Correa, G.[Guilherme], Assuncao, P.A.[Pedro A.], Agostini, L.V.[Luciano V.], da Silva Cruz, L.A.[Luis A.],
Complexity scalability for real-time HEVC encoders,
RealTimeIP(12), No. 1, June 2016, pp. 107-122.
Springer DOI 1606
BibRef
Earlier:
Four-step algorithm for early termination in HEVC inter-frame prediction based on decision trees,
VCIP14(65-68)
IEEE DOI 1504
computational complexity BibRef

Corrêa, G.[Guilherme], Assunção, P.A.[Pedro A.], Agostini, L.V.[Luciano V.], da Silva Cruz, L.A.[Luis A.],
Pareto-Based Method for High Efficiency Video Coding With Limited Encoding Time,
CirSysVideo(26), No. 9, September 2016, pp. 1734-1745.
IEEE DOI 1609
Business process re-engineering BibRef

da Silva, T.L., Agostini, L.V., da Silva Cruz, L.A.,
Complexity reduction of depth intra coding for 3D video extension of HEVC,
VCIP14(229-232)
IEEE DOI 1504
computational complexity BibRef

Jin, X.[Xin], Dai, Q.H.[Qiong-Hai],
Clustering-Based Content Adaptive Tiles Under On-chip Memory Constraints,
MultMed(18), No. 12, December 2016, pp. 2331-2344.
IEEE DOI 1612
Complexity theory HEVC BibRef

Wang, S., Zhou, D., Zhou, J., Yoshimura, T., Goto, S.,
VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications,
CirSysVideo(27), No. 2, February 2017, pp. 380-393.
IEEE DOI 1702
Bandwidth BibRef

Sousa, L.[Leonel], Roma, N.[Nuno],
Special issue on real-time energy-aware circuits and systems for HEVC and for its 3D and SVC extensions,
RealTimeIP(13), No. 1, March 2017, pp. 1-3.
WWW Link. 1704
BibRef

Grellert, M.[Mateus], Zatt, B.[Bruno], Shafique, M.[Muhammad], Bampi, S.[Sergio], Henkel, J.[Jörg],
Complexity control of HEVC encoders targeting real-time constraints,
RealTimeIP(13), No. 1, March 2017, pp. 5-24.
Springer DOI 1704
BibRef

Rodríguez-Sánchez, R.[Rafael], Quintana-Ortí, E.S.[Enrique S.],
Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors,
RealTimeIP(13), No. 1, March 2017, pp. 25-38.
WWW Link. 1704
BibRef

Saldanha, M.[Mário], Sanchez, G.[Gustavo], Zatt, B.[Bruno], Porto, M.[Marcelo], Agostini, L.[Luciano],
Energy-aware scheme for the 3D-HEVC depth maps prediction,
RealTimeIP(13), No. 1, March 2017, pp. 55-69.
WWW Link. 1704
BibRef

Sanchez, G.[Gustavo], Marcon, C.[César], Agostini, L.[Luciano],
Real-time scalable hardware architecture for 3D-HEVC bipartition modes,
RealTimeIP(13), No. 1, March 2017, pp. 71-83.
WWW Link. 1704
BibRef

Zhang, Y.H.[Yu-Hua], Wang, Y.[Yong], Zhu, C.[Ce], Lin, Y.B.[Yong-Bing], Zheng, J.H.[Jian-Hua],
Optimization of depth modeling modes in 3D-HEVC depth intra coding,
RealTimeIP(13), No. 1, March 2017, pp. 85-100.
WWW Link. 1704
Get Access BibRef

Hsu, P.K., Shen, C.A.,
The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems,
CirSysVideo(27), No. 5, May 2017, pp. 1091-1103.
IEEE DOI 1705
Complexity theory, Encoding, Filtering, Memory management, Throughput, Very large scale integration, Deblocking filter (DBF), High Efficiency Video Coding (HEVC), VLSI, memory BibRef

Liu, L.B.[Lei-Bo], Chen, Y.J.[Ying-Jie], Deng, C.C.[Chen-Chen], Yin, S.[Shouyi], Wei, S.J.[Shao-Jun],
Implementation of in-loop filter for HEVC decoder on reconfigurable processor,
IET-IPR(11), No. 9, September 2017, pp. 685-692.
DOI Link 1709
BibRef


Kufa, J., Kratochvil, T.,
Software and hardware HEVC encoding,
WSSIP17(1-5)
IEEE DOI 1707
Central Processing Unit, Encoding, Graphics processing units, High definition video, Image coding, HEVC, HM, NVENC, Turing encoder, x265 BibRef

Parois, R., Hamidouche, W., Mora, E.G., Raulet, M., Deforges, O.,
Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder,
DASIP16(11-17)
IEEE DOI 1704
parallel architectures BibRef

Gomez, A.[Augusto], Perea, J.[Jhon], Trujillo, M.[Maria],
Parallel Integer Motion Estimation for High Efficiency Video Coding (HEVC) Using OpenCL,
CIARP16(68-75).
Springer DOI 1703
BibRef

Gu, J., Han, Y., Wen, J.,
A novel low delay in-loop filtering WPP process for parallel HEVC encoding,
VCIP16(1-4)
IEEE DOI 1701
Delays BibRef

Igarashi, H., Takano, F., Moriyoshi, T.,
Highly parallel transformation and quantization for HEVC encoder on GPUs,
VCIP16(1-4)
IEEE DOI 1701
Acceleration BibRef

Kalali, E., Hamzaoglu, I.,
FPGA implementations of HEVC Inverse DCT using high-level synthesis,
DASIP15(1-6)
IEEE DOI 1605
discrete cosine transforms BibRef

Stabernack, B., Möller, J., Hahlbeck, J., Brandenburg, J.,
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support,
DASIP15(1-2)
IEEE DOI 1605
field programmable gate arrays BibRef

Baik, H.K.[Hyun-Ki], Song, H.[Hwangjun],
A complexity-based adaptive tile partitioning algorithm for HEVC decoder parallelization,
ICIP15(4298-4302)
IEEE DOI 1512
HEVC; Parallel Processing; Tile; Video coding BibRef

Abeydeera, M.[Maleen], Pasqual, A.[Ajith],
HEVC inverse transform architecture utilizing coefficient sparsity,
ICIP15(4848-4852)
IEEE DOI 1512
BibRef

Yu, Q.[Quanhe], Zheng, X.[Xiaozhen], Zheng, J.H.[Jian-Hua], He, Y.[Yun], Yu, W.[Wei], Wang, D.[Dadong], Chen, J.[Junyou], Xu, Y.Y.[Yang-Yang],
High-throughput and low-complexity binary arithmetic decoder based on logarithmic domain,
ICIP15(3305-3309)
IEEE DOI 1512
Arithmetic coding; CABAC; H.265/HEVC; LBAC; entropy coding BibRef

Maich, H.[Henrique], Paim, G.[Guilherme], Afonso, V.[Vladimir], Agostini, L.[Luciano], Zatt, B.[Bruno], Porto, M.[Marcelo],
A multi-standard interpolation hardware solution for H.264 and HEVC,
ICIP15(2910-2914)
IEEE DOI 1512
Fractional Motion Estimation; H.264; HEVC; Hardware Design BibRef

Bariani, M.[Massimo], Lambruschini, P.[Paolo], Raggio, M.[Marco], Pezzoni, L.[Luca],
An Efficient SIMD Implementation of the H.265 Decoder for Mobile Architecture,
QoEM15(563-570).
Springer DOI 1511
BibRef

Chen, G., Pei, Z., Liu, Z., Ikenaga, T.,
Deblocking strength prediction based CTU-level SAO category determination in HEVC encoder,
VCIP15(1-4)
IEEE DOI 1605
Bit rate BibRef

Jiang, Y.[Yuebing], Llamocca, D., Pattichis, M., Esakki, G.,
A unified and pipelined hardware architecture for implementing intra prediction in HEVC,
Southwest14(29-32)
IEEE DOI 1406
indexing BibRef

Karwowski, D.[Damian],
Improved Adaptive Arithmetic Coding for HEVC Video Compression Technology,
ICCVG12(121-128).
Springer DOI 1210
BibRef

Karwowski, D.[Damian], Domanski, M.[Marek],
Improved Context-Based Adaptive Binary Arithmetic Coding in MPEG-4 AVC/H.264 Video Codec,
ICCVG10(II: 25-32).
Springer DOI 1009
BibRef

Li, F.[Fu], Shi, G.M.[Guang-Ming], Wu, F.[Feng],
An efficient VLSI architecture for 4X4 intra prediction in the High Efficiency Video Coding (HEVC) standard,
ICIP11(373-376).
IEEE DOI 1201
BibRef

Sinangil, M.E.[Mahmut E.], Chandrakasan, A.P.[Anantha P.], Sze, V.[Vivienne], Zhou, M.H.[Min-Hua],
Hardware-aware motion estimation search algorithm development for high-efficiency video coding (HEVC) standard,
ICIP12(1529-1532).
IEEE DOI 1302
BibRef

Sinangil, M.E.[Mahmut E.], Chandrakasan, A.P.[Anantha P.], Sze, V.[Vivienne], Zhou, M.H.[Min-Hua],
Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine,
ICIP12(1533-1536).
IEEE DOI 1302
BibRef

Sze, V.[Vivienne], Chandrakasan, A.P.[Anantha P.], Budagavi, M.[Madhukar], Zhou, M.H.[Min-Hua],
Parallel CABAC for low power video coding,
ICIP08(2096-2099).
IEEE DOI 0810
BibRef

Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
Single Chip, Chipset for Coding .


Last update:Nov 18, 2017 at 20:56:18