5.5.10.3 Single Chip, Chipset for Coding

Chapter Contents (Back)
Hardware. VLSI.

Park, H.[Heonchul], Prasanna, V.K.,
Modular VLSI architectures for real-time full-search-based vector quantization,
CirSysVideo(3), No. 4, August 1993, pp. 309-317.
IEEE Top Reference. 0206
BibRef

Park, N.[Neungsoo], Bae, J.W.[Jong-Woo], Prasanna, V.K.,
Synthesis of VLSI architectures for tree-structured image coding,
ICIP96(II: 999-1002).
IEEE DOI 9610
BibRef

Bae, J.W.[Jong-Woo], Prasanna, V.K.,
A fast and area-efficient VLSI architecture for embedded image coding,
ICIP95(III: 452-455).
IEEE DOI 9510
BibRef

Goodenough, J., Meacham, R.J., Morris, J.D., Luke Seed, N., Ivey, P.A.,
A single chip video signal processing architecture for image processing, coding, and computer vision,
CirSysVideo(5), No. 5, October 1995, pp. 436-445.
IEEE Top Reference. 0206
BibRef
Earlier:
A general purpose, single chip video signal processing (VSP) architecture for image processing, coding and computer vision,
ICIP94(III: 601-605).
IEEE DOI 9411
BibRef

Sahinoglou, H., Cabrera, S.D.,
A high-speed pyramid image coding algorithm for a VLSI implementation,
CirSysVideo(1), No. 4, December 1991, pp. 369-374.
IEEE Top Reference. 0206
BibRef

Ruetz, P.A., Tong, P., Bailey, D., Luthi, P.A., Ang, P.H.,
A high-performance full-motion video compression chip set,
CirSysVideo(2), No. 2, June 1992, pp. 111-122.
IEEE Top Reference. 0206
BibRef

Fujiwara, H., Liou, M.L., Sun, M.T., Yang, K.M., Maruyama, M., Shomura, K., Ohyama, K.,
An all-ASIC implementation of a low bit-rate video codec,
CirSysVideo(2), No. 2, June 1992, pp. 123-134.
IEEE Top Reference. 0206
BibRef

Kraus, J., Reimers, J., Gruger, K.,
A VLSI chip set for DPCM coding of HDTV signals,
CirSysVideo(3), No. 4, August 1993, pp. 302-308.
IEEE Top Reference. 0206
BibRef

Nam, S.H., Lee, M.K.,
Flexible VLSI Architecture of Motion Estimator for Video Image Compression,
CirSysSignal(43), No. 6, June 1996, pp. 467-470. 9607
BibRef

Hasegawa, K., Ohara, K., Oka, A., Kamada, T., Nagaoka, Y., Yano, K., Yamauchi, E., Kashiro, T., Nakagawa, T.,
Low-Power Video Encoder/Decoder Chip Set for Digital VCRs,
SolidCir(31), No. 11, November 1996, pp. 1780-1788. 9611
BibRef

Kozek, T., Wu, C.W., Zarandy, A., Chen, H., Roska, T., Kunt, M., Chua, L.O.,
New Results and Measurements Related to Some Tasks in Object-Oriented Dynamic Image-Coding Using GNN Universal Chips,
CirSysVideo(7), No. 4, August 1997, pp. 606-614.
IEEE Top Reference. 9708
BibRef

Berns, J.P., Noll, T.G.,
A Flexible 200 GOPs HDTV Motion Estimation Chip,
VLSIVideo(19), No. 2, July 1998, pp. 85-95. 9809
BibRef

Yakovleff, A.J.S., Moini, A.,
Motion Perception Using Analog VLSI,
AICandSP(15), No. 2, February 1998, pp. 183-200. 9804
BibRef

Pirsch, P., Stolberg, H.J.,
VLSI Implementations of Image and Video Multimedia Processing Systems,
CirSysVideo(8), No. 7, November 1998, pp. 878.
IEEE Top Reference. BibRef 9811

Fatemi, O., Panchanathan, S.,
Fractal Engine: An Affine Video Processor Core for Multimedia Applications,
CirSysVideo(8), No. 7, November 1998, pp. 892.
IEEE Top Reference. BibRef 9811

Lai, Y.K., Lai, Y.L., Liu, Y.C., Wu, P.C., Chen, L.G.,
VLSI Implementation of the Motion Estimator with 2-Dimensional Data-Reuse,
Consumer(44), No. 3, August 1998, pp. 623-629. 9810
BibRef

Lei, M.H.[Ming-Han], Chiueh, T.D.[Tzi-Dar],
An analog motion field detection chip for image segmentation,
CirSysVideo(12), No. 5, May 2002, pp. 299-308.
IEEE Top Reference. 0206
BibRef

Hsia, S.C.[Shih-Chang],
VLSI implementation for low-complexity full-search motion estimation,
CirSysVideo(12), No. 7, July 2002, pp. 613-619.
IEEE Top Reference. 0208
BibRef

Efron, U., David, I., Sinelnikov, V., Apter, B.,
A CMOS/LCOS Image Transceiver Chip for Smart Goggle Applications,
CirSysVideo(14), No. 2, February 2004, pp. 269-273.
IEEE Abstract. 0403
BibRef

Xi, Y.L.[Ying-Lai], Hao, C.Y.[Chong-Yang], Fan, Y.Y.[Yang-Yu], Hu, H.Q.[Hong-Qi],
A fast block-matching algorithm based on adaptive search area and its VLSI architecture for H.264/AVC,
SP:IC(21), No. 8, September 2006, pp. 626-646.
WWW Link. 0609
H.264/AVC; VLSI; Motion estimation; Adaptive search area; Early termination; Pipelined BibRef


Dong, Y.[Yu], Omaki, R.Y., Onoye, T., Shirakawa, I.,
VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder,
ICIP00(Vol III: 126-129).
IEEE DOI 0008
BibRef

Yamada, K.[Keiichi], Soga, M.[Mineki],
A Motion Measurement Vision Chip,
ICIP99(IV:6-10).
IEEE DOI BibRef 9900

Jaspers, E.G.T.[Egbert G.T.], de With, P.H.N.[Peter H.N.],
Architecture of embedded video processing in a multimedia chip-set,
ICIP99(II:787-791).
IEEE DOI BibRef 9900

Lee, J.H.[Jae-Hun], Kim, S.D.[Sung Deuk], Jang, S.K.[Sung Kyu], Ra, J.B.[Jong Beom],
A New VLSI Architecture of a Hierarchical Motion Estimator for Low Bit-rate Video Coding,
ICIP99(II:774-778).
IEEE DOI BibRef 9900

Park, S.B., Teuner, A., Hosticaka, B.J.,
A motion detection system based on a CMOS photo sensor array,
ICIP98(III: 967-971).
IEEE DOI 9810
BibRef

Brockmeyer, E., Catthoor, F., Bormans, J., de Man, H.,
Code transformations for reduced data transfer and storage in low power realisations of MPEG-4 full-pel motion estimation,
ICIP98(III: 985-989).
IEEE DOI 9810
BibRef

Baglietto, P., Maresca, M., Migliaro, A., Migliardi, M.,
A VLSI scalable processor array for motion estimation,
CIAP95(127-132).
Springer DOI 9509
BibRef

Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
Multiple Description Video Coding .


Last update:Sep 18, 2017 at 11:34:11