19.2.9 Hardware, VLSI Implementations, Embedded Processors, Sensor Processing

Chapter Contents (Back)
Parallel Algorithms. Embedded Systems. VLSI.

Husain-Abidi, A.S.[Akram S.],
Design concepts for an on-board parallel image processor,
PR(5), No. 1, March 1973, pp. 3-10.
WWW Link. 0309
BibRef

Hwang, K.[Kai], and Su, S.P.[Shun-Piao],
VLSI Architectures for Feature Extraction and Pattern Classification,
CVGIP(24), No. 2, November 1983, pp. 215-228.
WWW Link. Some VLSI implementations for image processing algorithms. BibRef 8311

Yung, H.C., Allen, C.R.,
Optimal floating point multiplication processor for signal processing,
IVC(1), No. 3, August 1983, pp. 152-156.
WWW Link. 0401
BibRef

Nussmeier, T.A.[Thomas A.], Fouse, S.D.[Scott D.],
Image processing architecture,
US_Patent4,398,256, 08/09/1983.
HTML Version. BibRef 8308

Ranganath, H.S.,
Hardware Implementation of Image Registration Algorithms,
IVC(4), No. 3, August 1986, pp. 151-158.
WWW Link. BibRef 8608

Lodi, E., Pagli, L.,
A VLSI Solution to the Vertical Segment Visibility Problem,
TC(35), 1986, pp. 923-928. BibRef 8600

Chang, H.D., Fu, K.S.,
VLSI Architecture for Dynamic Time-Warp Recognition of Handwritten Symbols,
ASSP(34), 1986, pp. 603-613. BibRef 8600

Hatamian, M.,
A Real-Time Two-Dimensional Moment Generating Algorithm and Its Single Chip Implementation,
ASSP(34), 1986, pp. 546-553. BibRef 8600

Sugai, M., Kanuma, A., Suzuki, K., Kubo, M.,
VLSI Processor for Image Processing,
PIEEE(75), 1987, pp. 1160-1166. BibRef 8700

Cheng, H.D., Fu, K.S.,
VLSI architectures for string matching and pattern matching,
PR(20), No. 1, 1987, pp. 125-141.
WWW Link. 0309
BibRef

Rhodes, F.M., Dituri, J.J., Chapman, G.H., Emerson, B.E., Soares, A.M., and Raffel, J.I.,
A Monolithic Hough Transform Processor Based on Restructurable VLSI,
PAMI(10), No. 1, January 1988, pp. 106-110.
IEEE DOI Hough. BibRef 8801

Hanahara, K., Maruyama, T., and Uchiyama, T.,
A Real-Time Processor for the Hough Transform,
PAMI(10), No. 1, January 1988, pp. 121-125.
IEEE DOI Hough. Real Time, Hough. BibRef 8801

Bhanu, B., Hutchings, B.L., Smith, K.F.,
VLSI Design and Implementation of a Real-Time Image Segmentation Processor,
MVA(3), 1990, pp. 21-44. BibRef 9000

Ranganathan, N., Mehrotra, R.,
A VLSI architecture for dynamic scene analysis,
CVGIP(53), No. 2, March 1991, pp. 189-197.
WWW Link. 0501
BibRef
Earlier:
A VLSI architecture for difference picture-based dynamic scene analysis,
ICPR90(II: 506-508).
IEEE DOI 9208
BibRef

Ranganathan, N., Shah, M.,
A scale-space chip,
ICPR88(I: 420-424).
IEEE DOI 8811
BibRef

Liu, S.C., and Harris, J.,
Dynamic Wires: An Analog VLSI Model for Object-Based Processing,
IJCV(8), No. 3, 1992, pp. 231-239.
Springer DOI BibRef 9200

Deweerth, S.P.,
Analog VLSI Circuits for Stimulus Localization and Centroid Computation,
IJCV(8), No. 3, 1992, pp. 191-202.
Springer DOI BibRef 9200

Cheng, H.D., Tang, Y.Y., Suen, C.Y.,
Parallel image transformation and its VLSI implementation,
PR(23), No. 10, 1990, pp. 1113-1129.
WWW Link. 0401
BibRef

Tang, Y.Y.[Yuan Y.], Cheng, X., Tao, L.X.[Li-Xin], Suen, C.Y.[Ching Y.],
Parallel regional projection transformation (RPT) and VLSI implementation,
PR(26), No. 4, April 1993, pp. 627-641.
WWW Link. 0401
BibRef

Tang, Y.Y., Suen, C.Y.,
Parallel character recognition based on regional projection transformation (RPT),
ICPR92(II:631-634).
IEEE DOI 9208
BibRef

Athanas, P.M., and Abbott, A.L.,
Real-Time Image Processing on a Custom Computing Platform,
Computer(28), No. 2, February 1995, pp. 16-24. An S-Bus based system with 16 processors on each board for processing. BibRef 9502

Bernard, T.M., Nguyen, P.E., Devos, F.J., Zavidovique, B.Y.,
A Programmable VLSI Retina for Rough Vision,
MVA(7), 1993, pp. 4-11. BibRef 9300

Bernard, T.M., Zavidovique, B.Y.,
About the adjective 'neural', when applied to smart sensors,
ICPR90(II: 556-560).
IEEE DOI 9208
BibRef

Zavidovique, B.Y., Bernard, T.M.,
Generic functions for on-chip vision,
ICPR92(IV:1-10).
IEEE DOI 9208
BibRef

Tang, Y.Y., Suen, C.Y.,
RPCT Algorithm and its VLSI Implementation,
SMC(24), 1994, pp. 87-99. BibRef 9400

Cheng, H.D., and Cheng, X.,
Shape Recognition Using a Fixed-Size VLSI Architecture,
PRAI(9), 1995, pp. 1-21. BibRef 9500

Cheng, H.D., Fu, K.S.,
Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture,
PR(19), No. 5, 1986, pp. 361-372.
WWW Link. 0309
BibRef

Yamauchi, H., Tashiro, Y., Minami, T., Suzuki, Y.,
Architecture and implementation of a highly parallel single-chip video DSP,
CirSysVideo(2), No. 2, June 1992, pp. 207-220.
IEEE Top Reference. 0206
BibRef

Kwentus, A.Y., Werter, M.J., Willson, Jr., A.N.,
A programmable digital filter IC employing multiple processors on a single chip,
CirSysVideo(2), No. 2, June 1992, pp. 231-244.
IEEE Top Reference. 0206
BibRef

Miyazaki, T., Nishitani, T., Ishikawa, M., Edahiro, M., Mitsuhashi, K.,
Chrominance/luminance signal separation and syntheses chips developed with a DSP silicon compiler,
CirSysVideo(2), No. 2, June 1992, pp. 245-254.
IEEE Top Reference. 0206
BibRef

Banzato, L., Benvenuto, N., Cortelazzo, G.M.,
A design technique for two-dimensional multiplierless FIR filters for video applications,
CirSysVideo(2), No. 3, September 1992, pp. 273-284, 329-30.
IEEE Top Reference. 0206
BibRef

Alawa, M.N., Coulon, P.Y., Fristot, V., Grillo, C., Charras, J.P., Chehikian, A.,
An Open Bus Architecture for Real Time Video Applications,
RealTimeImg(4), No. 3, June 1998, pp. 217-228. 9807
BibRef

Sillitoe, I.P.W., Tombak, M.,
A Compact Look Up Table Structure for Low Level Binary Image Processing,
RealTimeImg(4), No. 3, June 1998, pp. 203-210. 9807
BibRef

Schaffer, M., Chen, T.,
A Tree Matching Algorithm and VLSI Architecture for Real Time 2D Object Classification,
RealTimeImg(4), No. 3, June 1998, pp. 193-202. 9807
BibRef

Ranganathan, N., Sastry, R., Venkatesan, R.,
SMAC: A VLSI Architecture for Scene Matching,
RealTimeImg(4), No. 3, June 1998, pp. 171-180. 9807
BibRef
Earlier: A3, A2, A1:
A VLSI architecture for hierarchical scene matching,
ICPR92(IV:214-217).
IEEE DOI 9208
BibRef

Dallaire, S., Tremblay, M., Poussart, D.,
Mixed-Signal VLSI Architecture for Real Time Computer Vision,
RealTimeImg(3), No. 5, October 1997, pp. 307-317. 9712
BibRef

Kubota, T., Huntsberger, T.L., Alford, C.O.,
A Vision System with Real Time Feature Extractor and Relaxation Network,
PRAI(12), No. 3, May 1998, pp. 335-354. 9807
BibRef

Cheng, H.D., Wu, C.Y., Hung, D.L.,
VLSI for Moment Computation and Its Application to Breast Cancer Detection,
PR(31), No. 9, September 1998, pp. 1391-1406.
WWW Link. 9808
BibRef

Kim, Y., Gove, R.J.,
Guest Editorial: Advanced Imaging Chip Architectures And Applications,
IJIST(9), No. 6, 1998, pp. 405-406. 9812
BibRef

Markandey, V., Rabadi, W., Golston, J., Frantz, G.,
Architectures and Visual-Processing Applications of Multimedia DSPs,
IJIST(9), No. 6, 1998, pp. 416-422. 9812
BibRef

Basoglu, C.[Chris], Gove, R.J.[Robert J.], Kojima, K.[Keiji], O'Donnell, J.[John],
Single-chip processor for media applications: the MAP1000TM,
IJIST(10), No. 1, 1999, pp. 96-106. BibRef 9900

Bensrhair, A., Chafiqui, N., Miché, P.,
Implementation of a 3D Vision System on DSPs TMS320C31,
RealTimeImg(6), No. 3, June 2000, pp. 213-221. 0008
BibRef

Chang, S., Kim, B.S., Kim, L.S.,
A Programmable 3.2-GOPS Merged DRAM Logic for Video Signal Processing,
CirSysVideo(10), No. 6, September 2000, pp. 967-973.
IEEE Top Reference. 0010
BibRef

Illgner, K.[Klaus],
DSPs for image and video processing,
SP(80), No. 11, November 2000, pp. 2323-2336. 0010
BibRef

Illgner, K., Gruber, H.G., Gelabert, P., Liang, J.[Jie], Yoo, Y.J.[Young-Jun], Rabadi, W., Talluri, R.,
Programmable DSP platform for digital still cameras,
ICASSP99(IV: 2235-2238).
IEEE DOI DSP chip for cameras. BibRef 9900

Mémin, É.[Étienne], Risset, T.[Tanguy],
VLSI Design Methodology for Edge-Preserving Image Reconstruction,
RealTimeImg(7), No. 1, February 2001, pp. 109-126.
DOI Link 0106
BibRef

Wiehler, K., Heers, J., Schnörr, C., Stiehl, H.S., Grigat, R.R.,
A One-Dimensional Analog VLSI Implementation for Nonlinear Real-Time Signal Preprocessing,
RealTimeImg(7), No. 1, February 2001, pp. 127-142.
DOI Link 0106
BibRef

Heers, J., Schnorr, C., Stiehl, H.S.,
Globally convergent iterative numerical schemes for nonlinear variational image smoothing and segmentation on a multiprocessor machine,
IP(10), No. 6, June 2001, pp. 852-864.
IEEE DOI 0106
BibRef
Earlier:
Investigation of parallel and globally convergent iterative schemes for nonlinear variational image smoothing and segmentation,
ICIP98(III: 279-283).
IEEE DOI 9810
BibRef

Maharatna, K., Dhar, A.S., Banerjee, S.[Swapna],
A VLSI array architecture for realization of DFT, DHT, DCT and DST,
SP(81), No. 9, September 2001, pp. 1813-1822.
HTML Version. 0110
For Hough alone: See also VLSI array architecture for Hough transform, A. BibRef

Wiatr, K.[Kazimierz],
Median and Morphological Specialized Processors for a Real-Time Image Data Processing,
JASP(2002), No. 1 2002, pp. 115.
WWW Link. BibRef 0200

Sohm, O.P.[Oliver P.], Bull, D.R.[David R.], Canagarajah, C.N.[C. Nishan],
Efficient methodology for hand-coding video algorithms for VLIW-type processors,
SP:IC(17), No. 4, April 2002, pp. 305-325.
WWW Link. 0205
BibRef

Handkiewicz, A.,
Two-dimensional switched capacitor filter design system for real-time image processing,
CirSysVideo(1), No. 3, September 1991, pp. 241-246.
IEEE Top Reference. 0206
BibRef

Umminger, C.B., Sodini, C.G.,
Switched capacitor networks for focal plane image processing systems,
CirSysVideo(2), No. 4, December 1992, pp. 392-400.
IEEE Top Reference. 0206
BibRef

Basoglu, C., Lee, W.B.[Woo-Bin], O'Donnell, J.,
The equator MAP-CA(TM)DSP: An end-to-end broadband signal processor(TM) VLIW,
CirSysVideo(12), No. 8, August 2002, pp. 646-659.
IEEE Top Reference. 0208
BibRef

Moshnyaga, V.G.,
Reducing energy dissipation of frame memory by adaptive bit-width compression,
CirSysVideo(12), No. 8, August 2002, pp. 713-718.
IEEE Top Reference. 0208
BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
High performance 2D parallel block-filtering system for real-time imaging applications using the Sharc ADSP21060,
RealTimeImg(9), No. 2, April 2003, pp. 151-161.
WWW Link. 0304
BibRef

McLernon, D.C.,
Relationship between an LPTV system and the equivalent LTI MIMO structure,
VISP(150), No. 3, June 2003, pp. 133-141.
IEEE Abstract. 0308
BibRef

Moini, A.[Alireza],
Vision Chips,
KluwerOctober 1999. ISBN 0-7923-8664-7
WWW Link. smart visual sensors, are those sensors that have integrated image acquisition and parallel processing, often at the pixel level, using dedicated analog and digital circuits. BibRef 9910

Roska, T.[Tamás], Rodriguez-Vazquez, A.,
Toward visual microprocessors,
PIEEE(90), No. 7, July 2002, pp. 1244-1257.
IEEE DOI 0207
BibRef

Roska, T.[Tamás],
The analogic single-chip CNN visual supercomputer: A review,
CAIP93(813-821).
Springer DOI 9309
BibRef

Wu, B.F.[Bing-Fei], Hu, Y.Q.[Yi-Qiang],
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters,
CirSysVideo(13), No. 9, September 2003, pp. 936-943.
IEEE Abstract. 0310
BibRef

Kessal, L., Abel, N., Demigny, D.,
Real-time image processing with dynamically reconfigurable architecture,
RealTimeImg(9), No. 5, October 2003, pp. 297-313.
WWW Link. 0311
BibRef

Kessal, L., Demigny, D., Boudouani, N., Bourgiba, R.,
Reconfigurable Hardware for Real Time Image Processing,
ICIP00(Vol III: 110-113).
IEEE DOI 0008
BibRef

Fürtler, J.[Johannes], Mayer, K.J.[Konrad J.], Krattenthaler, W.[Werner], Bajla, I.[Ivan],
SPOT: Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing,
RealTimeImg(9), No. 6, December 2003, pp. 387-399.
WWW Link. 0401
BibRef

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C., Chawathe, M.,
Accelerated image processing on FPGAs,
IP(12), No. 12, December 2003, pp. 1543-1551.
IEEE DOI 0402
BibRef
Earlier:
Implementing image applications on FPGAs,
ICPR02(III: 265-268).
IEEE DOI 0211
BibRef

Lu, C.K., Summerfield, S.,
Design and VLSI implementation of QMF banks,
VISP(151), No. 5, October 2004, pp. 421-427.
IEEE Abstract. 0501
BibRef

Huang, C.T., Tseng, P.C., Chen, L.G.,
Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform With Line-Based Method,
CirSysVideo(15), No. 7, July 2005, pp. 910-920.
IEEE DOI 0508
BibRef

Artyomov, E., Rivenson, Y., Levi, G., Yadid-Pecht, O.,
Morton (Z) Scan Based Real-Time Variable Resolution CMOS Image Sensor,
CirSysVideo(15), No. 7, July 2005, pp. 947-952.
IEEE DOI 0508
BibRef

Bishnu, A., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A., Acharya, T.,
Euler vector for search and retrieval of gray-tone images,
SMC-B(35), No. 4, August 2005, pp. 801-812.
IEEE DOI 0508
BibRef
Earlier:
On-chip Computation of Euler Number of a Binary Image for Efficient Database Search,
ICIP01(III: 310-313).
IEEE DOI 0108
BibRef

Bishnu, A., Bhunre, P.K., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A.,
Content Based Image Retrieval: Related Issues Using Euler Vector,
ICIP02(II: 585-588).
IEEE DOI 0210
BibRef

Bolcioni, L., Campi, F., Canegallo, R., Guerrieri, R.,
A low-power system-on-chip for the documentation of road accidents,
CirSysVideo(15), No. 11, November 2005, pp. 1493-1501.
IEEE DOI 0512
BibRef

Martina, M.[Maurizio], Masera, G.[Guido],
Mumford and Shah Functional: VLSI Analysis and Implementation,
PAMI(28), No. 3, March 2006, pp. 487-494.
IEEE DOI 0602
See also Optimal Approximations by Piecewise Smooth Functions and Variational Problems. BibRef

Reyna-Rojas, R.[Roberto], Houzet, D.[Dominique], Dragomirescu, D.[Daniela], Carlier, F.[Florent], Ouadjaout, S.[Salim],
Object Recognition System-on-Chip Using the Support Vector Machines,
JASP(2005), No. 7, 2005, pp. 993-1004.
WWW Link. 0603
BibRef

Barbaro, M.[Massimo], Raffo, L.[Luigi],
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities,
JASP(2005), No. 7, 2005, pp. 1062-1070.
WWW Link. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Choudhary, V.[Vishal], Broers, H.[Harry],
Scalable IC Platform for Smart Cameras,
JASP(2005), No. 13, 2005, pp. 2018-2025.
WWW Link. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Schueler, B.[Ben], Danilin, A.[Alexander],
Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing,
AVSBS07(69-74).
IEEE DOI 0709
BibRef
And: ICDSC07(109-116).
IEEE DOI 0709
BibRef

Fischer, V.[Viktor], Lukac, R.[Rastislav], Martin, K.[Karl],
Cost-Effective Video Filtering Solution for Real-Time Vision Systems,
JASP(2005), No. 13, 2005, pp. 2026-2042.
WWW Link. 0603
BibRef

Wang, D., Yu, N., Gao, Y., Zhang, R.,
Effective correlation vector quantisation algorithm and its VLSI architecture,
VISP(153), No. 6, December 2006, pp. 735-738.
DOI Link 0702
BibRef

Bensaali, F., Amira, A.,
Field programmable gate array based parallel matrix multiplier for 3D affine transformations,
VISP(153), No. 6, December 2006, pp. 739-746.
DOI Link 0702
BibRef

Dang, P.[Philip],
VLSI architecture for real-time image and video processing systems,
RealTimeIP(1), No. 1, October 2006, pp. 57-62.
Springer DOI 0001
BibRef

Dandekar, O.[Omkar], Castro-Pareja, C.[Carlos], Shekhar, R.[Raj],
FPGA-based real-time 3D image preprocessing for image-guided medical interventions,
RealTimeIP(1), No. 4, July 2007, pp. 285-301.
Springer DOI 0707
BibRef

Saponara, S.[Sergio], Fanucci, L.[Luca], Marsi, S.[Stefano], Ramponi, G.[Giovanni],
Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing,
RealTimeIP(1), No. 4, July 2007, pp. 267-283.
Springer DOI 0707
BibRef

Marsi, S.[Stefano], Ramponi, G.[Giovanni],
A flexible FPGA implementation for illuminance-reflectance video enhancement,
RealTimeIP(8), No. 1, March 2013, pp. 81-93.
WWW Link. 1303
BibRef

Saponara, S.[Sergio], Casula, M.[Michele], Fanucci, L.[Luca],
ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Marsi, S.[Stefano], Saponara, S.[Sergio],
Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design,
RealTimeIP(5), No. 4, December 2010, pp. 275-289.
WWW Link. 1101
BibRef

Saponara, S.[Sergio],
Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec,
RealTimeIP(7), No. 1, March 2012, pp. 43-53.
WWW Link. 1202
BibRef

Banerjee, S., Evans, B.L.,
In-Camera Automation of Photographic Composition Rules,
IP(16), No. 7, July 2007, pp. 1807-1820.
IEEE DOI 0707
BibRef

Cheng, C.C., Huang, C.T., Chen, C.Y., Lian, C.J., Chen, L.G.,
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform,
CirSysVideo(17), No. 7, July 2007, pp. 814-822.
IEEE DOI 0707
BibRef

Kumaki, T.[Takeshi], Kono, Y.[Yutaka], Ishizaki, M.[Masakatsu], Koide, T.[Tetsushi], Mattausch, H.J.[Hans Jürgen],
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory,
IEICE(E90-D), No. 1, January 2007, pp. 346-354.
DOI Link 0701
BibRef

Chandrasekaran, S.[Shrutisagar], Amira, A.[Abbes], Minghua, S.[Shi], Bermak, A.[Amine],
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Sriram, V.[Vinay], Kearney, D.[David],
Multiple parallel FPGA implementations of a Kolmogorov phase screen generator,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Chen, J.C., Chien, S.Y.,
CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders,
CirSysVideo(18), No. 9, September 2008, pp. 1223-1236.
IEEE DOI 0810
BibRef

Hiromoto, M.[Masayuki], Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
Partially Parallel Architecture for AdaBoost-Based Detection with Haar-Like Features,
CirSysVideo(19), No. 1, January 2009, pp. 41-52.
IEEE DOI 0902
See also Object Detection Based on Image Blur Using Spatial-Domain Filtering with Haar-Like Features. BibRef

Hiromoto, M.[Masayuki], Nakahara, K.[Kentaro], Sugano, H.[Hiroki], Nakamura, Y.[Yukihiro], Miyamoto, R.[Ryusuke],
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features,
EmbedCV07(1-8).
IEEE DOI 0706
BibRef

Razeghi, M., Hoffman, D., Nguyen, B.M., Delaunay, P.Y., Huang, E.K., Tidrow, M.Z., Nathan, V.,
Recent Advances in LWIR Type-II InAs/GaSb Superlattice Photodetectors and Focal Plane Arrays at the Center for Quantum Devices,
PIEEE(97), No. 6, June 2009, pp. 1056-1066.
IEEE DOI 0905
BibRef

Chaikalis, D.P., Sgouros, N.P., Maroulis, D.E.,
A real-time FPGA architecture for 3D reconstruction from integral images,
JVCIR(21), No. 1, January 2010, pp. 9-16.
Elsevier DOI 1002
Three-dimensional; Integral image; Image reconstruction; Image representation; Autostereoscopy; Architecture; Real-time; Hardware; FPGA BibRef

Gao, C., Lu, S.L.L., Suh, T., Lim, H.,
Field programmable gate array-ased haar classifier for accelerating face detection algorithm,
IET-IPR(4), No. 3, June 2010, pp. 184-194.
DOI Link 1006
BibRef

Kisacanin, B.[Branislav], Nikolic, Z.[Zoran],
Algorithmic and software techniques for embedded vision on programmable processors,
SP:IC(25), No. 5, June 2010, pp. 352-362.
Elsevier DOI 1007
Real-time; Embedded; Vision; Programmable; DSP BibRef

Krill, B., Ahmad, A., Amira, A., Rabah, H.,
An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores,
SP:IC(25), No. 5, June 2010, pp. 377-387.
Elsevier DOI 1007
BibRef
And: A1, A3, A2, A4:
A new FPGA-based dynamic partial reconfiguration design flow and environment for image processing applications,
EUVIP10(226-231).
IEEE DOI 1110
Dynamic partial reconfiguration (DPR); Design flow; Field programmable gate array (FPGA); IP cores; Image and signal processing BibRef

Ahmad, A.[Afandi], Amira, A.[Abbes], Nicholl, P.[Paul], Krill, B.[Benjamin],
FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration,
RealTimeIP(8), No. 3, September 2013, pp. 327-340.
Springer DOI 1309
BibRef

Ahmad, A., Amira, A., Guarisco, M., Rabah, H., Berviller, Y.,
Efficient implementation of a 3-D medical imaging compression system using CAVLC,
ICIP10(3773-3776).
IEEE DOI 1009
BibRef

Karthigaikumar, P., Baskaran, K.,
Partially Pipelined VLSI Implementation Of Blowfish Encryption/decryption Algorithm,
IJIG(10), No. 3, July 2010, pp. 327-341.
DOI Link 1003
BibRef

Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
Highly optimized implementation of OpenCV for the Cell Broadband Engine,
CVIU(114), No. 11, November 2010, pp. 1273-1281.
Elsevier DOI 1011
BibRef
Earlier:
A Real-Time Object Recognition System on Cell Broadband Engine,
PSIVT07(932-943).
Springer DOI 0712
Embedded processor (Sony playstation). 18fps for 8 targets. Image processing; OpenCV; Parallel implementation; Cell Broadband Engine BibRef

Jordan, H.[Harald], van Dyck, W.[Walter], Smodic, R.[Rene],
A co-processed contour tracing algorithm for a smart camera,
RealTimeIP(6), No. 1, March 2011, pp. 23-31.
WWW Link. 1103
BibRef

Tseng, Y.C., Hsu, P.H., Chang, T.S.,
A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering,
IP(20), No. 11, November 2011, pp. 3231-3241.
IEEE DOI 1110
BibRef

Chen, S.L., Huang, H.Y., Luo, C.H.,
A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications,
CirSysVideo(21), No. 11, November 2011, pp. 1600-1611.
IEEE DOI 1111
BibRef

Chen, S.L., Huang, H.Y., Luo, C.H.,
Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images,
CirSysVideo(21), No. 11, November 2011, pp. 1612-1621.
IEEE DOI 1111
BibRef

Chen, S.L.,
VLSI Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications,
CirSysVideo(23), No. 9, 2013, pp. 1510-1522.
IEEE DOI 1309
Algorithm design and analysis BibRef

Chen, S.L.[Shih-Lun], Ma, E.D.[En-Di],
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications,
CirSysVideo(24), No. 11, November 2014, pp. 1982-1991.
IEEE DOI 1411
VLSI BibRef

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Memory-Efficient Architecture for Hysteresis Thresholding and Object Feature Extraction,
IP(20), No. 12, December 2011, pp. 3566-3579.
IEEE DOI 1112
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And:
High-performance asic architecture for hysteresis thresholding and component feature extraction in limited-resource applications,
ICIP11(1061-1064).
IEEE DOI 1201
hysteresis thresholding avoided in streaming processing. BibRef

Rahman, A.A.H.A.[Ab Al-Hadi Ab], Prihozhy, A.[Anatoly], Mattavelli, M.[Marco],
Pipeline synthesis and optimization of FPGA-based video processing applications with CAL,
JIVP(2011), No. 1 2011, pp. xx-yy.
DOI Link 1203
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Huang, C.C.[Chien-Chuan], Chen, P.Y.[Pei-Yin], Ma, C.H.[Ching-Hsuan],
A Novel Interpolation Chip for Real-Time Multimedia Applications,
CirSysVideo(22), No. 10, October 2012, pp. 1512-1525.
IEEE DOI 1210
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Park, J.S., Kim, H.E., Kim, L.S.,
A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-mu-m CMOS Technology,
CirSysVideo(23), No. 5, May 2013, pp. 832-845.
IEEE DOI 1305
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Chen, J.[Jienan], Hu, J.[Jianhao],
High Throughput Stochastic Log-MAP Turbo-Decoder Based on Low Bits Computation,
SPLetters(20), No. 11, 2013, pp. 1098-1101.
IEEE DOI 1310
CMOS integrated circuits BibRef

Genovese, M., Napoli, E.,
FPGA-based architecture for real time segmentation and denoising of HD video,
RealTimeIP(8), No. 4, December 2013, pp. 389-401.
WWW Link. 1312
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Brost, V.[Vincent], Yang, F.[Fan], Meunier, C.[Charles],
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RealTimeIP(9), No. 1, March 2014, pp. 47-59.
WWW Link. 1403
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Granados, S.[Sara], Barranco, F.[Francisco], Mota, S.[Sonia], Díaz, J.[Javier], Ros, E.[Eduardo],
On-chip semidense representation map for dense visual features driven by attention processes,
RealTimeIP(9), No. 1, March 2014, pp. 171-185.
Springer DOI 1403
condense features to allow for processing on chip BibRef

Wang, J.H.[Jian-Hui], Zhong, S.[Sheng], Yan, L.[Luxin], Cao, Z.G.[Zhi-Guo],
An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching,
CirSysVideo(24), No. 3, March 2014, pp. 525-538.
IEEE DOI 1404
computational complexity BibRef

Jiang, J., Li, X., Zhang, G.,
SIFT Hardware Implementation for Real-Time Image Feature Extraction,
CirSysVideo(24), No. 7, July 2014, pp. 1209-1220.
IEEE DOI 1407
Computer architecture BibRef

Madanayake, A.[Arjuna], Wimalagunarathne…, R.[Randeel],
VLSI architecture for 4-D depth filtering,
SIViP(9), No. 4, May 2015, pp. 809-818.
WWW Link. 1504
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Schlessman, J.[Jason], Wolf, M.[Marilyn],
Tailoring Design for Embedded Computer Vision Applications,
Computer(48), No. 5, May 2015, pp. 58-62.
IEEE DOI 1506
Algorithm design and analysis BibRef

Belyaev, E., Liu, K., Gabbouj, M., Li, Y.,
An Efficient Adaptive Binary Range Coder and Its VLSI Architecture,
CirSysVideo(25), No. 8, August 2015, pp. 1435-1446.
IEEE DOI 1508
Encoding BibRef

Belyaev, E., Forchhammer, S., Liu, K.,
An Adaptive Multialphabet Arithmetic Coding Based on Generalized Virtual Sliding Window,
SPLetters(24), No. 7, July 2017, pp. 1034-1038.
IEEE DOI 1706
adaptive codes, arithmetic codes, probability, adaptive multialphabet arithmetic coding, compression performance, generalized virtual sliding window, multialphabet multiplication-free adaptive arithmetic coder, multiplication-free binary arithmetic coders, probability adaptation speed, probability estimation, Decoding, Encoding, Estimation, Indexes, Radiation detectors, Registers, Signal processing algorithms, Multialphabet arithmetic coding, probability, estimation BibRef

Zhou, T., Dong, T., Su, Y., He, Y.,
A CMOS Readout With High-Precision and Low-Temperature-Coefficient Background Current Skimming for Infrared Focal Plane Array,
CirSysVideo(25), No. 8, August 2015, pp. 1447-1455.
IEEE DOI 1508
Arrays BibRef

Maggiani, L., Bourrasset, C., Petracca, M., Berry, F., Pagano, P., Salvadori, C.,
HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing,
SPLetters(22), No. 11, November 2015, pp. 2132-2136.
IEEE DOI 1509
feature extraction BibRef

Fu, X.N.[Xiao-Ning], Wang, J.[Jie],
Algorithm and code optimizations for real-time passive ranging by imaging detection on single DSP,
SIViP(9), No. 6, September 2015, pp. 1377-1386.
Springer DOI 1509
Real time implementation of SIFT matching. BibRef

Pedre, S.[Sol], Krajník, T.[Tomáš], Todorovich, E.[Elías], Borensztejn, P.[Patricia],
Accelerating embedded image processing for real time: a case study,
RealTimeIP(11), No. 2, February 2016, pp. 349-374.
Springer DOI 1602
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Tomasi, M.[Matteo], Pundlik, S.[Shrinivas], Luo, G.[Gang],
FPGA-DSP co-processing for feature tracking in smart video sensors,
RealTimeIP(11), No. 4, April 2016, pp. 751-767.
WWW Link. 1604
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Monroe, D.[Don],
Silicon Photonics: Ready to Go the Distance?,
CACM(59), No. 5, May 2016, pp. 26-28.
DOI Link 1605
CMOS for optical circuits BibRef

Zhu, W., Liu, L., Jiang, G., Yin, S., Wei, S.,
A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator,
CirSysVideo(26), No. 8, August 2016, pp. 1532-1543.
IEEE DOI 1609
CMOS integrated circuits BibRef

Sérot, J.[Jocelyn], Berry, F.[François], Bourrasset, C.[Cédric],
High-level dataflow programming for real-time image processing on smart cameras,
RealTimeIP(12), No. 4, December 2016, pp. 635-647.
Springer DOI 1612
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Pelissier, F.[Frantz], Chenini, H.[Hanen], Berry, F.[François], Landrault, A.[Alexis], Derutin, J.P.[Jean-Pierre],
Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods,
RealTimeIP(12), No. 4, December 2016, pp. 663-679.
Springer DOI 1612
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Müller, J.[Jens], Müller, J.[Jan], Tetzlaff, R.[Ronald],
NEROvideo: a general-purpose CNN-UM video processing system,
RealTimeIP(12), No. 4, December 2016, pp. 763-774.
Springer DOI 1612
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Ye, L.H.[Li-Hua], Yao, K.[Keqi], Hang, J.J.[Jian-Jun], Tu, P.P.[Ping-Ping], Cui, Y.[Yiping],
A hardware solution for real-time image acquisition systems based on GigE camera,
RealTimeIP(12), No. 4, December 2016, pp. 827-834.
Springer DOI 1612
More the issue of how much processing is required to get the image and what to do about that. BibRef

Meyer-Baese, U.[Uwe], Meyer-Baese, A.[Anke], González, D.[Diego], Botella, G.[Guillermo], García, C.[Carlos], Prieto-Matías, M.[Manuel],
Code obfuscation using very long identifiers for FFT motion estimation models in embedded processors,
RealTimeIP(11), No. 4, April 2016, pp. 817-827.
Springer DOI 1604
Protecting the code on devices. BibRef

Ackerman, E.,
Motion-planning chip speeds robots,
Spectrum(54), No. 1, January 2017, pp. 9-10.
IEEE DOI 1702
grippers BibRef

Nnolim, U.A.[Uche A.],
FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid Color Image Enhancement System,
IJIG(17), No. 01, 2017, pp. 1750004.
DOI Link 1703
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Huang, J.J.[Jing-Jin], Zhou, G.Q.[Guo-Qing],
On-Board Detection and Matching of Feature Points,
RS(9), No. 6, 2017, pp. xx-yy.
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FPGA-based method. BibRef

Sahlbach, H.[Henning], Thiele, D.[Daniel], Ernst, R.[Rolf],
A system-level FPGA design methodology for video applications with weakly-programmable hardware components,
RealTimeIP(13), No. 2, June 2017, pp. 291-309.
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Ratnayake, K.[Kumara], Amer, A.[Aishy],
Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling,
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Mathew, M., Desappan, K., Swami, P.K., Nagori, S.,
Sparse, Quantized, Full Frame CNN for Low Power Embedded Devices,
ECVW17(328-336)
IEEE DOI 1709
Complexity theory, Digital signal processing, Quantization (signal), Streaming media, Tensile stress, Training, Tuning BibRef

Roy, F., Mamdy, B., Ahmed, N., Tournier, A., Lu, G.N.,
Development of small-sized pixel structures for high-resolution CMOS image sensors,
ICIVC17(494-500)
IEEE DOI 1708
Crosstalk, Dark current, Diffusion tensor imaging, Optical crosstalk, Passivation, Photodiodes, Transistors, 2T pixel architecture, MOS capacitor deep trench isolation (CDTI), P-type and N-type pixel options, back-side illumination (BSI), single-transistor pixel, vertical, photodiode BibRef

Choi, Y., Park, J.S., Kim, L.S.,
Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph Cut in Resistor Grid,
WACV17(778-786)
IEEE DOI 1609
Algorithm design and analysis, Fuses, Hardware, Mobile communication, Resistors, Robots, Visualization BibRef

Hadj Salem, K., Kieffer, Y., Mancini, S.,
Memory management in embedded vision systems: Optimization problems and solution methods,
DASIP16(200-207)
IEEE DOI 1704
computer vision BibRef

Xia, T.[Tian], Rihani, M.A.F., Prévotet, J.C., Nouvel, F.,
Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable accelerators management,
DASIP16(225-226)
IEEE DOI 1704
embedded systems BibRef

Sau, C., Fanni, T., Meloni, P., Raffo, L., Pelcat, M., Palumbo, F.,
Demo: Reconfigurable Platform Composer Tool,
DASIP16(245-246)
IEEE DOI 1704
embedded systems BibRef

Basterretxea, K., Martinez-Corral, U., Finker, R., del Campo, I.,
ELM-based hyperspectral imagery processor for onboard real-time classification,
DASIP16(43-50)
IEEE DOI 1704
geophysical image processing BibRef

Tan, B., Biglari-Abhari, M., Salcic, Z.,
A system-level security approach for heterogeneous MPSoCs,
DASIP16(74-81)
IEEE DOI 1704
embedded systems BibRef

Bollengier, T., Najem, M., Le Lann, J.C., Lagadec, L.,
Demo: Overlay architectures for heterogeneous FPGA cluster management,
DASIP16(239-240)
IEEE DOI 1704
fault tolerant computing BibRef

Desoli, G.[Giuseppe], Tomaselli, V.[Valeria], Plebani, E.[Emanuele], Urlini, G.[Giulio], Pau, D.[Danilo], D'Alto, V.[Viviana], Majo, T.[Tommaso], De Ambroggi, F.[Fabio], Boesch, T.[Thomas], Singh, S.P.[Surinder-Pal], Guidetti, E.[Elio], Chawla, N.[Nitin],
The Orlando Project: A 28 nm FD-SOI Low Memory Embedded Neural Network ASIC,
ACIVS16(217-227).
Springer DOI 1611
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Werner, S., Stiehle, B., Becker, J.,
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip,
DASIP15(1-6)
IEEE DOI 1605
digital signal processing chips BibRef

MATIP: A dynamic hardware task integration platform for Multiprocessing Reconfigurable System on Chip,
DASIP15(1-6)
IEEE DOI 1605
distributed memory systems BibRef

Cyriac, P.[Praveen], Kane, D.[David], Bertalmio, M.[Marcelo],
Perceptual Dynamic Range for In-Camera Image Processing,
BMVC15(xx-yy).
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FPGA acceleration for feature based processing applications,
ECVW15(42-47)
IEEE DOI 1510
Acceleration BibRef

Fresse, V., Ge, Z.W.[Zhi-Wei], Tan, J.Y.[Jun-Yan], Rousseau, F.,
Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platforms,
IPTA12(435-441)
IEEE DOI 1503
field programmable gate arrays Network-On-Chip architecture. BibRef

Ekstrand, F.[Fredrik], Ahlberg, C.[Carl], Ekström, M.[Mikael], Spampinato, G.[Giacomo],
Towards an Embedded Real-Time High Resolution Vision System,
ISVC14(II: 541-550).
Springer DOI 1501
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Shoaib, S.[Saad], Hafiz, R.[Rehan], Shafique, M.[Muhammad],
Hardware/Software Co-design of Embedded Real-Time KD-Tree Based Feature Matching Systems,
ISVC14(II: 936-945).
Springer DOI 1501
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Góngora-Martín, C., Castillo-Atoche, A., Estrada-López, J., Vázquez-Castillo, J., Ortegón-Aguilar, J., Carrasco-Álvarez, R.,
Hybrid FPGA/ARM Co-design for Near Real Time of Remote Sensing Imagery,
CASI14(1039-1046).
Springer DOI 1411
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Rentería-Cedano, J.A., Aguilar-Lobo, L.M., Ortega-Cisneros, S., Loo-Yau, J.R., Raygoza-Panduro, J.J.[Juan J.],
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems,
CIARP14(88-95).
Springer DOI 1411
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Eibensteiner, F.[Florian], Kogler, J.[Juergen], Scharinger, J.[Josef],
A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform,
ECVW14(637-644)
IEEE DOI 1409
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Zhou, G.[Guyue], Liu, A.[Ang], Yang, K.[Kang], Wang, T.[Tao], Li, Z.[Zexiang],
An Embedded Solution to Visual Mapping for Consumer Drones,
ECVW14(670-675)
IEEE DOI 1409
embedded vision; sensor fusion; visual mapping BibRef

Zhang, B.[Buyue], Appia, V.[Vikram], Pekkucuksen, I.[Ibrahim], Liu, Y.C.[Yu-Cheng], Batur, A.U.[Aziz Umit], Shastry, P.[Pavan], Liu, S.[Stanley], Sivasankaran, S.J.[Shi-Ju], Chitnis, K.[Kedar],
A Surround View Camera Solution for Embedded Systems,
ECVW14(676-681)
IEEE DOI 1409
ADAS BibRef

Ladig, R.[Robert], Shimonomura, K.[Kazuhiro],
FPGA-Based Fast Response Image Analysis for Autonomous or Semi-autonomous Indoor Flight,
ECVW14(682-687)
IEEE DOI 1409
Aerial robotics; FPGA; Monocular vision; Onboard vision; Quadrotor BibRef

Thieling, L.[Lothar], Schuer, A.[Andre], Hartung, G.[Georg], Buchel, G.[Gregor],
Embedded image processing system for cloud-based applications,
WSSIP14(163-166) 1406
Cameras BibRef

Hamilton, L., Parker, D., Yu, C., Indyk, P.,
Focal plane array folding for efficient information extraction and tracking,
AIPR12(1-6)
IEEE DOI 1307
analogue-digital conversion BibRef

Rajesvari, R., Manoj, G., Ponrani, M.A.[M. Angelin], Joy, M.A.[Merin Annie],
IP core based architecture of telecommand System-on-Chip (SoC) for spacecraft applications,
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IEEE DOI 1304
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ICPR12(2266-2269).
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Bartovsky, J.[Jan], Dokladalova, E.[Eva], Dokladal, P.[Petr], Akil, M.[Mohamed],
Efficient FPGA architecture for oriented 1-D opening and pattern spectrum,
ICIP12(1689-1692).
IEEE DOI 1302
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Said, Y.[Yahia], Saidani, T.[Taoufik], Smach, F.[Fethi], Atri, M.[Mohamed], Snoussi, H.[Hichem],
Embedded Real-Time Video Processing System on FPGA,
ICISP12(85-92).
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Fast PDE-Based Image Analysis in Your Pocket,
SSVM11(544-555).
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FPGA design for image processing using a GUI of a web-based VHDL Code Generator,
VCIP11(1).
IEEE DOI 1201
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Chong, W.[Wang], Hong, Z.[Zheng], Zhen, L.[Li],
Hardware/software co-design of embedded image processing system using systemc modeling platform,
IASP11(524-528).
IEEE DOI 1112
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IEEE DOI 1106
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IEEE DOI 1106
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ECVW11(123-128).
IEEE DOI 1106
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IEEE DOI 1106
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System on Chip Coprocessors for High Speed Image Feature Detection and Matching,
ACIVS11(599-610).
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Bit-plane stack filter algorithm for focal plane processors,
ICIP10(3741-3744).
IEEE DOI 1009
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Real Time Hot Spot Detection Using FPGA,
CIARP09(595-602).
Springer DOI 0911
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Design of Reconfigurable LED Illumination Control System Based on FPGA,
CISP09(1-4).
IEEE DOI 0910
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IEEE DOI 1006
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EmbedCV09(878-885).
IEEE DOI 0910
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A feasible VLSI engine for soft-input-soft-output for joint source channel codes,
ICIP09(2669-2672).
IEEE DOI 0911
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IPTA10(529-534).
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FPGA memory optimization for real-time imaging,
DASIP16(176-182)
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cache storage BibRef

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IPTA08(1-8).
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ICISP08(498-507).
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ICDSC07(372-378).
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Litzenberger, M., Belbachir, A.N., Schon, P., Posch, C.,
Embedded Smart Camera for High Speed Vision,
ICDSC07(81-86).
IEEE DOI 0709
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A Low-Cost, Tiled Embedded Smart Camera System for Computer Vision Applications,
ICDSC07(125-131).
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Fast scale invariant feature detection and matching on programmable graphics hardware,
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Integral Image Optimizations for Embedded Vision Applications,
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Stein, G.P., Rushinek, E., Hayun, G., Shashua, A.,
A Computer Vision System on a Chip: A case study from the automotive domain,
EmbedCV05(III: 130-130).
IEEE DOI 0507
BibRef

Chang, C.J.[Chi-Jeng], Wu, W.T.[Wu-Ting], Su, H.C.[Hui-Ching], Huang, Z.Y.[Zen-Yi], Li, H.Y.[Hsin-Yen],
ARM Based Microcontroller for Image Capturing in FPGA Design,
ISVC05(672-677).
Springer DOI 0512
BibRef

Bertalmio, M., Fort, P., Sanchez-Crespo, D.,
Real-time, accurate depth of field using anisotropic diffusion and programmable graphics cards,
3DPVT04(767-773).
IEEE DOI 0412
BibRef

Elouardi, A., Bouaziz, S., Dupret, A., Klein, J.O., Reynaud, R.,
On chip vision system architecture using a CMOS retina,
IVS04(206-211).
WWW Link. 0411
BibRef

Woetzel, J., Koch, R.,
Multi-camera real-time depth estimation with discontinuity handling on PC graphics hardware,
ICPR04(I: 741-744).
IEEE DOI 0409
BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
Three-dimensional digital filtering algorithm for parallel DSP implementation,
ICIP03(II: 579-582).
IEEE DOI 0312
BibRef

Laffely, A., Liang, J.[Jian], Tessier, R., Burleson, W.,
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores,
ICIP03(III: 105-108).
IEEE DOI 0312
BibRef

Michell, J.A., Ruiz, G.A., Buron, A.M.,
Parallel-pipelined architecture for 2-D ICT VLSI implementation,
ICIP03(III: 89-92).
IEEE DOI 0312
BibRef

Lv, T., Ozer, B., Wolf, W.,
Exploiting parallelism in media processing using VLIW processor,
ICIP03(III: 97-100).
IEEE DOI 0312
BibRef

Lee, S.W.[Seong-Whan], Lee, S.W.[Sang-Woong], Jung, H.C.[Ho-Choul],
Real-Time Implementation of Face Recognition Algorithms on DSP Chip,
AVBPA03(294-301).
Springer DOI 0310
BibRef

van der Wal, G.S.[Gooitzen S.], Hsu, S.[Steve], Matei, B.C.[Bogdan C.],
Video Analysis using the Acadia I(TM) Single-Chip Vision System,
CVPR01(Demos 19-20). 0110
BibRef

McCurry, P., Morgan, F., Kilmartin, L.,
Xilinx FPGA Implementation of an Image Classifier for Object Detection Applications,
ICIP01(III: 346-349).
IEEE DOI 0108
BibRef

Vlassis, S., Fikos, G., Siskos, S.,
A Floating Gate CMOS Euclidean Distance Calculator and Its Application to Hand-written Digit Recognition,
ICIP01(III: 350-353).
IEEE DOI 0108
BibRef

McCanny, P., Masud, S., McCanny, J.,
An Efficient Architecture for the 2-d Biorthogonal Discrete Wavelet Transform,
ICIP01(III: 314-317).
IEEE DOI 0108
BibRef

Draper, B.A., Böhm, A.P.W.[A.P. Willem], Hammes, J., Najjar, W., Beveridge, J.R., Ross, C., Chawathe, M., Desai, M., Bins, J.,
Compiling SA-C Programs to FPGAs: Performance Results,
CVS01(220-235).
Springer DOI 0106
BibRef

Sudharsanan, S., Sriram, P., Frederickson, H., Gulati, A.,
Image and Video Processing Using MAJC 5200,
ICIP00(Vol III: 122-125).
IEEE DOI 0008
BibRef

Ooi, R., Hamamoto, T., Naemura, T., Aizawa, K.,
Pixel Independent Random Access Image Sensor for Real Time Image-based Rendering System,
ICIP01(II: 193-196).
IEEE DOI 0108
BibRef

Hamamoto, T.[Takayuki], Ooi, R.[Ryutaro], Ohtsuka, Y.[Yasuhiro], Aizawa, K.[Kiyoharu],
Real-Time Image Processing by Using Image Compression Sensor,
ICIP99(III:935-939).
IEEE DOI BibRef 9900

Peng, W.S.[Wen-Shiaw], Lee, C.Y.[Chen-Yi],
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform,
ICIP99(II:754-758).
IEEE DOI BibRef 9900

Sousa, L.[Leonel],
Applying Conditional Processing to Design Low-Power Array Processors for Motion Estimation,
ICIP99(II:769-773).
IEEE DOI BibRef 9900

Ishikawa, M.[Masatoshi],
1ms VLSI Vision Chip System and Its Applications,
AFGR98(214-219).
IEEE DOI BibRef 9800

Sicard, G., Bouvier, G., Lelah, A.,
A Light Adaptive 4000 Pixels Analog Silicon Retina for Edge Extraction and Motion Detection,
MVA98(xx-yy). BibRef 9800

Benedetti, A.[Arrigo], Perona, P.[Pietro],
Real-Time 2-D Feature Detection on a Reconfigurable Computer,
CVPR98(586-593).
IEEE DOI BibRef 9800

Redford, J.,
A three Giga-op DSP chip for image processing,
ICIP98(III: 981-984).
IEEE DOI 9810
BibRef

Muramatsu, S., Kobayashi, Y., Araoka, M., Naoi, S., Kaneta, T., Hirose, K., Onizawa, S.,
Image processing LSI 'ISP-IV' based on local parallel architecture and its applications,
ICIP98(III: 1000-1004).
IEEE DOI 9810
BibRef

Gokstorp, M., Forchheimer, R.,
Smart vision sensors,
ICIP98(I: 479-482).
IEEE DOI 9810
BibRef

Spirig, T., Seitz, P., Vietze, O., Heitger, F., Kubler, O.,
Real-time 2D feature detection with low-level image processing algorithms on smart CCD/CMOS image sensors,
ICIP96(II: 1043-1046).
IEEE DOI 9610
BibRef

Chen, C.C.[Chih-Chin], Jen, C.W.[Chein-Wei],
A programmable concurrent video signal processor,
ICIP96(II: 1039-1042).
IEEE DOI 9610
BibRef

Sorel, Y.,
Real-time embedded image processing applications using the A3 methodology,
ICIP96(II: 145-148).
IEEE DOI 9610
BibRef

Ker, J.S.[Jar-Shone], Kuo, Y.H.[Yau-Hwang], Liu, B.D.[Bin-Da],
Design of a color reproduction neural network chip with on-chip learning capability,
ICIP96(II: 1023-1026).
IEEE DOI 9610
BibRef

Chen, C.L.[Chao-Lieh], Lee, C.S.[Chang-Shing], Kuo, Y.H.[Yau-Hwang],
Design of high speed weighted fuzzy mean filters with generic LR fuzzy cells,
ICIP96(II: 1027-1030).
IEEE DOI 9610
BibRef

Dallaire, S., Poussart, D., Tremblay, M.,
Low Level Segmentation Using CMOS Smart Hexagonal Image Sensor,
CAMP95(xx). BibRef 9500

Pechanek, G.G., Stojancic, M., Vassiliadis, S., Glossner, C.J.,
MFAST: a single chip highly parallel image processing architecture,
ICIP95(I: 69-72).
IEEE DOI 9510
BibRef

Muller, S.,
A new programmable VLSI architecture for histogram and statistics computation in different windows,
ICIP95(I: 73-76).
IEEE DOI 9510
BibRef

Potkonjak, M.,
Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations,
ICIP95(I: 77-80).
IEEE DOI 9510
BibRef

Olstad, B., Steen, E., Halaas, A.,
Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering,
ICIP95(II: 113-116).
IEEE DOI 9510
BibRef

Ranganathan, N., Venygopal, S.[Satish],
An Efficient VLSI Architecture for Template Matching Based on Moment Preserving Pattern Matching,
ICPR94(C:388-390).
IEEE DOI BibRef 9400

Tremblay, M., Savard, M., Poussart, D.,
Medium Level Scene Representation Using VLSI Smart Hexagonal Sensor with multi-resolution Edge Extraction Capability and Scale Space Integration Co-Processor,
CVPR94(632-637).
IEEE DOI BibRef 9400

Yates, R.B., Evans, S.J., Ivey, P.A.,
A 1.2 billion operations per second video signal processing chip,
ICIP94(III: 596-600).
IEEE DOI 9411
BibRef

Thacker, N.A., Courtney, P., Walker, S.N., Evans, S.J., Yates, R.B.,
Specification and design of a general purpose image processing chip,
ICPR94(C:268-273).
IEEE DOI 9410
BibRef

Stout, M.G., Salmon, L.G., Rudolph, G.L., Martinez, T.R.,
A VLSI implementation of a parallel, self-organizing learning model,
ICPR94(C:373-376).
IEEE DOI 9410
BibRef

Chen, S.[Sarit], Ginosar, R.,
Adaptive sensitivity CCD image sensor,
ICPR94(C:363-365).
IEEE DOI 9410
BibRef

Kabir, I., Hsieh, M., Donovan, W., Jabbi, A., Radke, W.,
Programmable image processing in a memory controller,
ICIP94(III: 672-677).
IEEE DOI 9411
BibRef

Tang, Y.Y., Cheng, X., Tao, L., Suen, C.Y., Talaat, M., Inglese, R.,
VLSI architecture for parallel concentration-contour approach,
ICPR92(IV:151-154).
IEEE DOI 9208
BibRef

Courtney, P.[Patrick], Thacker, N.A.[Neil A.], Brown, C.R.[Chris R.],
Hardware support for fast edge-based stereo,
ECCV92(902-906).
Springer DOI 9205
BibRef
And:
A Hardware Architecture for Image Rectification and Ground Plane Obstacle Detection,
ICPR92(IV:23-26).
IEEE DOI BibRef

Dron, L.,
System-level design of specialized VLSI hardware for computing relative orientation,
WACV92(128-135).
WWW Link. 0403
BibRef

Patel, M., McCabe, P.A., Ranganathan, N.,
SIBA: a VLSI systolic array chip for image processing,
ICPR92(IV:15-18).
IEEE DOI 9208
BibRef

Sundaresan, V.K., Nichani, S., Ranganathan, N., Sankar, R.,
A VLSI hardware accelerator for dynamic time warping,
ICPR92(IV:27-30).
IEEE DOI 9208
BibRef

Botha, T.H.,
An analog CMOS programmable and configurable neural network,
ICPR92(IV:222-224).
IEEE DOI 9208
BibRef

Ishiyama, Y., Funaoka, C., Kubo, F., Takahashi, H., Tomita, F.,
Labeling board based on boundary tracking,
ICPR92(IV:34-38).
IEEE DOI 9208
Hardware implementation. BibRef

Fukushima, T.,
A survey of image processing LSIs in Japan,
ICPR90(II: 394-401).
IEEE DOI 9208
BibRef

Mao, W.D., Kung, S.Y.,
An object recognition system using stochastic knowledge source and VLSI parallel architecture,
ICPR90(I: 832-836).
IEEE DOI 9006
BibRef

Gijbels, T., van Eycken, L., Oosterlinck, A., Note, S., Catthoor, F.,
An ASIC-architecture for VLSI-implementation of the RBN-algorithm,
ICPR90(II: 408-412).
IEEE DOI 9208
BibRef

Chen, K., Astrom, A., Danielsson, P.E.,
PASIC: a smart sensor for computer vision,
ICPR90(II: 286-291).
IEEE DOI 9208
BibRef

Tremblay, M., Poussart, D.,
MAR: an integrated system for focal plane edge tracking with parallel analog processing and built-in primitives for image acquisition and analysis,
ICPR90(II: 292-298).
IEEE DOI 9208
BibRef

Klein, J.C., Collange, F., Bilodeau, M.,
A bit plane architecture for an image analysis processor implemented with P.L.C.A. gate array,
ECCV90(33-49).
Springer DOI 9004
BibRef

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Pipelined Processors and Algorithms .


Last update:Sep 18, 2017 at 11:34:11