19.2.8 Hardware, VLSI Implementations, Processors, Sensor Processing

Husain-Abidi, A.S.[Akram S.],
Design concepts for an on-board parallel image processor,
PR(5), No. 1, March 1973, pp. 3-10.
WWW Version. 0309 BibRef

Hwang, K.[Kai], and Su, S.P.[Shun-Piao],
VLSI Architectures for Feature Extraction and Pattern Classification,
CVGIP(24), No. 2, November 1983, pp. 215-228.
WWW Version. Some VLSI implementations for image processing algorithms. BibRef 8311

Yung, H.C., Allen, C.R.,
Optimal floating point multiplication processor for signal processing,
IVC(1), No. 3, August 1983, pp. 152-156.
WWW Version. 0401 BibRef

Nussmeier, T.A.[Thomas A.], Fouse, S.D.[Scott D.],
Image processing architecture,
US_Patent4,398,256, 08/09/1983.
HTML Version. BibRef 8308

Ranganath, H.S.,
Hardware Implementation of Image Registration Algorithms,
IVC(4), No. 3, August 1986, pp. 151-158.
WWW Version. BibRef 8608

Lodi, E., Pagli, L.,
A VLSI Solution to the Vertical Segment Visibility Problem,
TC(35), 1986, pp. 923-928. BibRef 8600

Chang, H.D., Fu, K.S.,
VLSI Architecture for Dynamic Time-Warp Recognition of Handwritten Symbols,
ASSP(34), 1986, pp. 603-613. BibRef 8600

Hatamian, M.,
A Real-Time Two-Dimensional Moment Generating Algorithm and Its Single Chip Implementation,
ASSP(34), 1986, pp. 546-553. BibRef 8600

Sugai, M., Kanuma, A., Suzuki, K., Kubo, M.,
VLSI Processor for Image Processing,
PIEEE(75), 1987, pp. 1160-1166. BibRef 8700

Cheng, H.D., Fu, K.S.,
VLSI architectures for string matching and pattern matching,
PR(20), No. 1, 1987, pp. 125-141.
WWW Version. 0309 BibRef

Rhodes, F.M., Dituri, J.J., Chapman, G.H., Emerson, B.E., Soares, A.M., and Raffel, J.I.,
A Monolithic Hough Transform Processor Based on Restructurable VLSI,
PAMI(10), No. 1, January 1988, pp. 106-110.
IEEE Abstract. IEEE Top Reference.
WWW Version. Hough. BibRef 8801

Hanahara, K., Maruyama, T., and Uchiyama, T.,
A Real-Time Processor for the Hough Transform,
PAMI(10), No. 1, January 1988, pp. 121-125.
IEEE Abstract. IEEE Top Reference.
WWW Version. Hough. Real Time, Hough. BibRef 8801

Bhanu, B., Hutchings, B.L., Smith, K.F.,
VLSI Design and Implementation of a Real-Time Image Segmentation Processor,
MVA(3), 1990, pp. 21-44. BibRef 9000

Ranganathan, N., Mehrotra, R.,
A VLSI architecture for dynamic scene analysis,
CVGIP(53), No. 2, March 1991, pp. 189-197.
WWW Version. 0501 BibRef
Earlier:
A VLSI architecture for difference picture-based dynamic scene analysis,
ICPR90(II: 506-508).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Ranganathan, N., Shah, M.,
A scale-space chip,
ICPR88(I: 420-424).
IEEE DOI may work or IEEE-CS DOI may work. 8811 BibRef

Liu, S.C., and Harris, J.,
Dynamic Wires: An Analog VLSI Model for Object-Based Processing,
IJCV(8), No. 3, 1992, pp. 231-239.
WWW Version. BibRef 9200

Deweerth, S.P.,
Analog VLSI Circuits for Stimulus Localization and Centroid Computation,
IJCV(8), No. 3, 1992, pp. 191-202.
WWW Version. BibRef 9200

Cheng, H.D., Tang, Y.Y., Suen, C.Y.,
Parallel image transformation and its VLSI implementation,
PR(23), No. 10, 1990, pp. 1113-1129.
WWW Version. 0401 BibRef

Tang, Y.Y.[Yuan Y.], Cheng, X., Tao, L.X.[Li-Xin], Suen, C.Y.[Ching Y.],
Parallel regional projection transformation (RPT) and VLSI implementation,
PR(26), No. 4, April 1993, pp. 627-641.
WWW Version. 0401 BibRef

Tang, Y.Y., Suen, C.Y.,
Parallel character recognition based on regional projection transformation (RPT),
ICPR92(II:631-634).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Athanas, P.M., and Abbott, A.L.,
Real-Time Image Processing on a Custom Computing Platform,
Computer(28), No. 2, February 1995, pp. 16-24. An S-Bus based system with 16 processors on each board for processing. BibRef 9502

Bernard, T.M., Nguyen, P.E., Devos, F.J., Zavidovique, B.Y.,
A Programmable VLSI Retina for Rough Vision,
MVA(7), 1993, pp. 4-11. BibRef 9300

Bernard, T.M., Zavidovique, B.Y.,
About the adjective 'neural', when applied to smart sensors,
ICPR90(II: 556-560).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Zavidovique, B.Y., Bernard, T.M.,
Generic functions for on-chip vision,
ICPR92(IV:1-10).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Tang, Y.Y., Suen, C.Y.,
RPCT Algorithm and its VLSI Implementation,
SMC(24), 1994, pp. 87-99. BibRef 9400

Cheng, H.D., and Cheng, X.,
Shape Recognition Using a Fixed-Size VLSI Architecture,
PRAI(9), 1995, pp. 1-21. BibRef 9500

Cheng, H.D., Fu, K.S.,
Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture,
PR(19), No. 5, 1986, pp. 361-372.
WWW Version. 0309 BibRef

Yamauchi, H., Tashiro, Y., Minami, T., Suzuki, Y.,
Architecture and implementation of a highly parallel single-chip video DSP,
CirSysVideo(2), No. 2, June 1992, pp. 207-220.
IEEE Top Reference. 0206 BibRef

Kwentus, A.Y., Werter, M.J., Willson, Jr., A.N.,
A programmable digital filter IC employing multiple processors on a single chip,
CirSysVideo(2), No. 2, June 1992, pp. 231-244.
IEEE Top Reference. 0206 BibRef

Miyazaki, T., Nishitani, T., Ishikawa, M., Edahiro, M., Mitsuhashi, K.,
Chrominance/luminance signal separation and syntheses chips developed with a DSP silicon compiler,
CirSysVideo(2), No. 2, June 1992, pp. 245-254.
IEEE Top Reference. 0206 BibRef

Banzato, L., Benvenuto, N., Cortelazzo, G.M.,
A design technique for two-dimensional multiplierless FIR filters for video applications,
CirSysVideo(2), No. 3, September 1992, pp. 273-284, 329-30.
IEEE Top Reference. 0206 BibRef

Alawa, M.N., Coulon, P.Y., Fristot, V., Grillo, C., Charras, J.P., Chehikian, A.,
An Open Bus Architecture for Real Time Video Applications,
RealTimeImg(4), No. 3, June 1998, pp. 217-228. 9807 BibRef

Sillitoe, I.P.W., Tombak, M.,
A Compact Look Up Table Structure for Low Level Binary Image Processing,
RealTimeImg(4), No. 3, June 1998, pp. 203-210. 9807 BibRef

Schaffer, M., Chen, T.,
A Tree Matching Algorithm and VLSI Architecture for Real Time 2D Object Classification,
RealTimeImg(4), No. 3, June 1998, pp. 193-202. 9807 BibRef

Ranganathan, N., Sastry, R., Venkatesan, R.,
SMAC: A VLSI Architecture for Scene Matching,
RealTimeImg(4), No. 3, June 1998, pp. 171-180. 9807 BibRef
Earlier: A3, A2, A1:
A VLSI architecture for hierarchical scene matching,
ICPR92(IV:214-217).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Dallaire, S., Tremblay, M., Poussart, D.,
Mixed-Signal VLSI Architecture for Real Time Computer Vision,
RealTimeImg(3), No. 5, October 1997, pp. 307-317. 9712 BibRef

Kubota, T., Huntsberger, T., Alford, C.O.,
A Vision System with Real Time Feature Extractor and Relaxation Network,
PRAI(12), No. 3, May 1998, pp. 335-354. 9807 BibRef

Cheng, H.D., Wu, C.Y., Hung, D.L.,
VLSI for Moment Computation and Its Application to Breast Cancer Detection,
PR(31), No. 9, September 1998, pp. 1391-1406.
WWW Version. 9808 BibRef

Kim, Y., Gove, R.J.,
Guest Editorial: Advanced Imaging Chip Architectures And Applications,
IJIST(9), No. 6, 1998, pp. 405-406. 9812 BibRef

Markandey, V., Rabadi, W., Golston, J., Frantz, G.,
Architectures and Visual-Processing Applications of Multimedia DSPs,
IJIST(9), No. 6, 1998, pp. 416-422. 9812 BibRef

Basoglu, C.[Chris], Gove, R.J.[Robert J.], Kojima, K.[Keiji], O'Donnell, J.[John],
Single-chip processor for media applications: the MAP1000TM,
IJIST(10), No. 1, 1999, pp. 96-106. BibRef 9900

Bensrhair, A., Chafiqui, N., Miché, P.,
Implementation of a 3D Vision System on DSPs TMS320C31,
RealTimeImg(6), No. 3, June 2000, pp. 213-221. 0008 BibRef

Chang, S., Kim, B.S., Kim, L.S.,
A Programmable 3.2-GOPS Merged DRAM Logic for Video Signal Processing,
CirSysVideo(10), No. 6, September 2000, pp. 967-973.
IEEE Top Reference. 0010 BibRef

Illgner, K.[Klaus],
DSPs for image and video processing,
SP(80), No. 11, November 2000, pp. 2323-2336. 0010 BibRef

Illgner, K., Gruber, H.G., Gelabert, P., Liang, J.[Jie], Yoo, Y.[Youngjun], Rabadi, W., Talluri, R.,
Programmable DSP platform for digital still cameras,
ICASSP99(IV: 2235-2238).
IEEE DOI may work or IEEE-CS DOI may work. DSP chip for cameras. BibRef 9900

Mémin, É.[Étienne], Risset, T.[Tanguy],
VLSI Design Methodology for Edge-Preserving Image Reconstruction,
RealTimeImg(7), No. 1, February 2001, pp. 109-126.
WWW Version. 0106 BibRef

Wiehler, K., Heers, J., Schnörr, C., Stiehl, H.S., Grigat, R.R.,
A One-Dimensional Analog VLSI Implementation for Nonlinear Real-Time Signal Preprocessing,
RealTimeImg(7), No. 1, February 2001, pp. 127-142.
WWW Version. 0106 BibRef

Heers, J., Schnorr, C., Stiehl, H.S.,
Globally convergent iterative numerical schemes for nonlinear variational image smoothing and segmentation on a multiprocessor machine,
IP(10), No. 6, June 2001, pp. 852-864.
IEEE DOI may work or IEEE-CS DOI may work. 0106 BibRef
Earlier:
Investigation of parallel and globally convergent iterative schemes for nonlinear variational image smoothing and segmentation,
ICIP98(III: 279-283).
IEEE DOI may work or IEEE-CS DOI may work. 9810 BibRef

Maharatna, K., Dhar, A.S., Banerjee, S.[Swapna],
A VLSI array architecture for realization of DFT, DHT, DCT and DST,
SP(81), No. 9, September 2001, pp. 1813-1822.
HTML Version. 0110For Hough alone: See also VLSI array architecture for Hough transform, A. BibRef

Wiatr, K.[Kazimierz],
Median and Morphological Specialized Processors for a Real-Time Image Data Processing,
JASP(2002), No. 1 2002, pp. 115. 0201
HTML Version. BibRef

Sohm, O.P.[Oliver P.], Bull, D.R.[David R.], Canagarajah, C.N.[C. Nishan],
Efficient methodology for hand-coding video algorithms for VLIW-type processors,
SP:IC(17), No. 4, April 2002, pp. 305-325.
WWW Version. 0205 BibRef

Handkiewicz, A.,
Two-dimensional switched capacitor filter design system for real-time image processing,
CirSysVideo(1), No. 3, September 1991, pp. 241-246.
IEEE Top Reference. 0206 BibRef

Umminger, C.B., Sodini, C.G.,
Switched capacitor networks for focal plane image processing systems,
CirSysVideo(2), No. 4, December 1992, pp. 392-400.
IEEE Top Reference. 0206 BibRef

Basoglu, C., Lee, W.B.[Woo-Bin], O'Donnell, J.,
The equator MAP-CA(TM)DSP: An end-to-end broadband signal processor(TM) VLIW,
CirSysVideo(12), No. 8, August 2002, pp. 646-659.
IEEE Top Reference. 0208 BibRef

Moshnyaga, V.G.,
Reducing energy dissipation of frame memory by adaptive bit-width compression,
CirSysVideo(12), No. 8, August 2002, pp. 713-718.
IEEE Top Reference. 0208 BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
High performance 2D parallel block-filtering system for real-time imaging applications using the Sharc ADSP21060,
RealTimeImg(9), No. 2, April 2003, pp. 151-161.
WWW Version. 0304 BibRef

McLernon, D.C.,
Relationship between an LPTV system and the equivalent LTI MIMO structure,
VISP(150), No. 3, June 2003, pp. 133-141.
IEEE Abstract. IEEE Top Reference. 0308 BibRef

Moini, A.[Alireza],
Vision Chips,
KluwerOctober 1999. ISBN 0-7923-8664-7
WWW Version. BibRef 9910

Roska, T.[Tamás], Rodriguez-Vazquez, A.,
Toward visual microprocessors,
PIEEE(90), No. 7, July 2002, pp. 1244-1257.
IEEE DOI may work or IEEE-CS DOI may work. 0207 BibRef

Roska, T.[Tamás],
The analogic single-chip CNN visual supercomputer: A review,
CAIP93(813-821).
WWW Version. 9309 BibRef

Wu, B.F.[Bing-Fei], Hu, Y.Q.A.[Yi-Qi-Ang],
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters,
CirSysVideo(13), No. 9, September 2003, pp. 936-943.
IEEE Abstract. IEEE Top Reference. 0310 BibRef

Kessal, L., Abel, N., Demigny, D.,
Real-time image processing with dynamically reconfigurable architecture,
RealTimeImg(9), No. 5, October 2003, pp. 297-313.
WWW Version. 0311 BibRef

Kessal, L., Demigny, D., Boudouani, N., Bourgiba, R.,
Reconfigurable Hardware for Real Time Image Processing,
ICIP00(Vol III: 110-113).
IEEE Abstract. IEEE Top Reference. 0008 BibRef

Fürtler, J.[Johannes], Mayer, K.J.[Konrad J.], Krattenthaler, W.[Werner], Bajla, I.[Ivan],
SPOT: Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing,
RealTimeImg(9), No. 6, December 2003, pp. 387-399.
WWW Version. 0401 BibRef

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C., Chawathe, M.,
Accelerated image processing on FPGAs,
IP(12), No. 12, December 2003, pp. 1543-1551.
IEEE DOI may work or IEEE-CS DOI may work. 0402 BibRef
Earlier:
Implementing image applications on FPGAs,
ICPR02(III: 265-268).
IEEE DOI may work or IEEE-CS DOI may work. 0211 BibRef

Lu, C.K., Summerfield, S.,
Design and VLSI implementation of QMF banks,
VISP(151), No. 5, October 2004, pp. 421-427.
IEEE Abstract. IEEE Top Reference. 0501 BibRef

Huang, C.T., Tseng, P.C., Chen, L.G.,
Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform With Line-Based Method,
CirSysVideo(15), No. 7, July 2005, pp. 910-920.
IEEE DOI may work or IEEE-CS DOI may work. 0508 BibRef

Artyomov, E., Rivenson, Y., Levi, G., Yadid-Pecht, O.,
Morton (Z) Scan Based Real-Time Variable Resolution CMOS Image Sensor,
CirSysVideo(15), No. 7, July 2005, pp. 947-952.
IEEE DOI may work or IEEE-CS DOI may work. 0508 BibRef

Bishnu, A., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A., Acharya, T.,
Euler vector for search and retrieval of gray-tone images,
SMC-B(35), No. 4, August 2005, pp. 801-812.
IEEE DOI may work or IEEE-CS DOI may work. 0508 BibRef
Earlier:
On-chip Computation of Euler Number of a Binary Image for Efficient Database Search,
ICIP01(III: 310-313).
IEEE Abstract. IEEE Top Reference. 0108 BibRef

Bishnu, A., Bhunre, P.K., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A.,
Content Based Image Retrieval: Related Issues Using Euler Vector,
ICIP02(II: 585-588).
IEEE Abstract. IEEE Top Reference. 0210 BibRef

Bolcioni, L., Campi, F., Canegallo, R., Guerrieri, R.,
A low-power system-on-chip for the documentation of road accidents,
CirSysVideo(15), No. 11, November 2005, pp. 1493-1501.
IEEE DOI may work or IEEE-CS DOI may work. 0512 BibRef

Martina, M.[Maurizio], Masera, G.[Guido],
Mumford and Shah Functional: VLSI Analysis and Implementation,
PAMI(28), No. 3, March 2006, pp. 487-494.
IEEE DOI may work or IEEE-CS DOI may work. 0602 See also Optimal Approximations by Piecewise Smooth Functions and Variational Problems. BibRef

Reyna-Rojas, R.[Roberto], Houzet, D.[Dominique], Dragomirescu, D.[Daniela], Carlier, F.[Florent], Ouadjaout, S.[Salim],
Object Recognition System-on-Chip Using the Support Vector Machines,
JASP(2005), No. 7, 2005, pp. 993-1004.
WWW Version. 0603 BibRef

Barbaro, M.[Massimo], Raffo, L.[Luigi],
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities,
JASP(2005), No. 7, 2005, pp. 1062-1070.
WWW Version. 0603 BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Choudhary, V.[Vishal], Broers, H.[Harry],
Scalable IC Platform for Smart Cameras,
JASP(2005), No. 13, 2005, pp. 2018-2025.
WWW Version. 0603 BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Schueler, B.[Ben], Danilin, A.[Alexander],
Camera mote with a high-performance parallel processor for real-time frame-based video processing,
AVSBS07(69-74).
IEEE DOI may work or IEEE-CS DOI may work. 0709 BibRef

Fischer, V.[Viktor], Lukac, R.[Rastislav], Martin, K.[Karl],
Cost-Effective Video Filtering Solution for Real-Time Vision Systems,
JASP(2005), No. 13, 2005, pp. 2026-2042.
WWW Version. 0603 BibRef

Wang, D., Yu, N., Gao, Y., Zhang, R.,
Effective correlation vector quantisation algorithm and its VLSI architecture,
VISP(153), No. 6, December 2006, pp. 735-738.
WWW Version. 0702 BibRef

Bensaali, F., Amira, A.,
Field programmable gate array based parallel matrix multiplier for 3D affine transformations,
VISP(153), No. 6, December 2006, pp. 739-746.
WWW Version. 0702 BibRef

Dang, P.[Philip],
VLSI architecture for real-time image and video processing systems,
RealTimeIP(1), No. 1, October 2006, pp. 57-62.
WWW Version. 0001 BibRef

Dandekar, O.[Omkar], Castro-Pareja, C.[Carlos], Shekhar, R.[Raj],
FPGA-based real-time 3D image preprocessing for image-guided medical interventions,
RealTimeIP(1), No. 4, July 2007, pp. 285-301.
WWW Version. 0707 BibRef

Saponara, S.[Sergio], Fanucci, L.[Luca], Marsi, S.[Stefano], Ramponi, G.[Giovanni],
Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing,
RealTimeIP(1), No. 4, July 2007, pp. 267-283.
WWW Version. 0707 BibRef

Saponara, S.[Sergio], Casula, M.[Michele], Fanucci, L.[Luca],
ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
WWW Version. 0804 BibRef

Banerjee, S., Evans, B.L.,
In-Camera Automation of Photographic Composition Rules,
IP(16), No. 7, July 2007, pp. 1807-1820.
IEEE DOI may work or IEEE-CS DOI may work. 0707 BibRef

Cheng, C.C., Huang, C.T., Chen, C.Y., Lian, C.J., Chen, L.G.,
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform,
CirSysVideo(17), No. 7, July 2007, pp. 814-822.
IEEE DOI may work or IEEE-CS DOI may work. 0707 BibRef

Kumaki, T.[Takeshi], Kono, Y.[Yutaka], Ishizaki, M.[Masakatsu], Koide, T.[Tetsushi], Mattausch, H.J.[Hans Jürgen],
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory,
IEICE(E90-D), No. 1, January 2007, pp. 346-354.
WWW Version. 0701 BibRef

Chandrasekaran, S.[Shrutisagar], Amira, A.[Abbes], Minghua, S.[Shi], Bermak, A.[Amine],
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
WWW Version. 0804 BibRef

Sriram, V.[Vinay], Kearney, D.[David],
Multiple parallel FPGA implementations of a Kolmogorov phase screen generator,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
WWW Version. 0804 BibRef

Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
A Real-Time Object Recognition System on Cell Broadband Engine,
PSIVT07(932-943).
WWW Version. 0712Embedded processor (Sony playstation). 18fps for 8 targets. BibRef

Wang, B.J.[Bang-Ju], Zhang, H.G.[Huan-Guo], Wang, Z.Y.[Zhang-Yi], Wang, Y.H.[Yu-Hua],
Speeding Up Scalar Multiplication Using a New Signed Binary Representation for Integers,
MCAM07(277-285).
WWW Version. 0706 BibRef

Lai, M.C.[Ming-Che], Guo, J.J.[Jian-Jun], Lv, Y.S.[Ya-Suai], Dai, K.[Kui], Wang, Z.Y.[Zhi-Ying],
The Research of an Embedded Processor Element for Multimedia Domain,
MCAM07(267-276).
WWW Version. 0706 BibRef

Baumgartner, D.[Daniel], Rossler, P.[Peter], Kubinger, W.[Wilfried],
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms,
EmbedCV07(1-8).
IEEE DOI may work or IEEE-CS DOI may work. 0706 BibRef

Hiromoto, M.[Masayuki], Nakahara, K.[Kentaro], Sugano, H.[Hiroki], Nakamura, Y.[Yukihiro], Miyamoto, R.[Ryusuke],
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features,
EmbedCV07(1-8).
IEEE DOI may work or IEEE-CS DOI may work. 0706 BibRef

Gabriel, R.C., Gomes, J., de Mello, M.J.C., Haas, H.L., Petraglia, A.,
New Error Sensitivity Model for the Analog Hardware Implementation of Inner Products,
ICIP06(3333-3336). 0610
IEEE DOI may work or IEEE-CS DOI may work. BibRef

Rowe, A., Goode, A.G., Goel, D., and Nourbakhsh, I.,
CMUcam3: An Open Programmable Embedded Vision Sensor,
CMU-RI-TR-07-13, May, 2007.
WWW Version. BibRef 0705

Rowe, A., Rosenberg, C., Nourbakhsh, I.,
A Second Generation Low Cost Embedded Color Vision System,
EmbedCV05(III: 136-136).
IEEE DOI may work or IEEE-CS DOI may work. 0507 BibRef

Gong, M.L.[Ming-Lun], Langille, A.[Aaron], Gong, M.[Mingwei],
Real-Time Image Processing Using Graphics Hardware: A Performance Study,
ICIAR05(1217-1225).
WWW Version. 0509 BibRef

Jodoin, P.M.[Pierre-Marc], Mignotte, M.[Max], St-Amour, J.F.[Jean-François],
Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware,
CIAP05(592-603).
WWW Version. 0509 BibRef

Kisacanin, B.[Branislav],
Integral Image Optimizations for Embedded Vision Applications,
Southwest08(181-184).
IEEE DOI may work or IEEE-CS DOI may work. 0803 BibRef
Earlier:
Examples of Low-Level Computer Vision on Media Processors,
EmbedCV05(III: 135-135).
IEEE DOI may work or IEEE-CS DOI may work. 0507 BibRef

Cabani, C.[Cristina], MacLean, W.J.[W. James],
A Proposed Pipelined-Architecture for FPGA-Based Affine-Invariant Feature Detectors,
EmbedCV06(121).
IEEE DOI may work or IEEE-CS DOI may work. 0609 BibRef

MacLean, W.J.,
An Evaluation of the Suitability of FPGAs for Embedded Vision Systems,
EmbedCV05(III: 131-131).
IEEE DOI may work or IEEE-CS DOI may work. 0507 BibRef

Stein, G.P., Rushinek, E., Hayun, G., Shashua, A.,
A Computer Vision System on a Chip: A case study from the automotive domain,
EmbedCV05(III: 130-130).
IEEE DOI may work or IEEE-CS DOI may work. 0507 BibRef

Chang, C.J.[Chi-Jeng], Wu, W.T.[Wu-Ting], Su, H.C.[Hui-Ching], Huang, Z.Y.[Zen-Yi], Li, H.Y.[Hsin-Yen],
ARM Based Microcontroller for Image Capturing in FPGA Design,
ISVC05(672-677).
WWW Version. 0512 BibRef

Bertalmio, M., Fort, P., Sanchez-Crespo, D.,
Real-time, accurate depth of field using anisotropic diffusion and programmable graphics cards,
3DPVT04(767-773).
IEEE Abstract. IEEE Top Reference. 0412 BibRef

Elouardi, A., Bouaziz, S., Dupret, A., Klein, J.O., Reynaud, R.,
On chip vision system architecture using a CMOS retina,
IVS04(206-211).
IEEE Abstract. IEEE Top Reference. 0411 BibRef

Woetzel, J., Koch, R.,
Multi-camera real-time depth estimation with discontinuity handling on PC graphics hardware,
ICPR04(I: 741-744).
IEEE DOI may work or IEEE-CS DOI may work. 0409 BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
Three-dimensional digital filtering algorithm for parallel DSP implementation,
ICIP03(II: 579-582).
IEEE Abstract. IEEE Top Reference. 0312 BibRef

Laffely, A., Liang, J.[Jian], Tessier, R., Burleson, W.,
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores,
ICIP03(III: 105-108).
IEEE Abstract. IEEE Top Reference. 0312 BibRef

Michell, J.A., Ruiz, G.A., Buron, A.M.,
Parallel-pipelined architecture for 2-D ICT VLSI implementation,
ICIP03(III: 89-92).
IEEE Abstract. IEEE Top Reference. 0312 BibRef

Lv, T., Ozer, B., Wolf, W.,
Exploiting parallelism in media processing using VLIW processor,
ICIP03(III: 97-100).
IEEE Abstract. IEEE Top Reference. 0312 BibRef

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Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Pipelined Processors and Algorithms .