20.2.9.1 Hardware Implementations, FPGA, Image Processing

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C., Chawathe, M.,
Accelerated image processing on FPGAs,
IP(12), No. 12, December 2003, pp. 1543-1551.
IEEE DOI 0402
BibRef
Earlier:
Implementing image applications on FPGAs,
ICPR02(III: 265-268).
IEEE DOI 0211
BibRef

Dandekar, O.[Omkar], Castro-Pareja, C.[Carlos], Shekhar, R.[Raj],
FPGA-based real-time 3D image preprocessing for image-guided medical interventions,
RealTimeIP(1), No. 4, July 2007, pp. 285-301.
Springer DOI 0707
BibRef

Marsi, S.[Stefano], Ramponi, G.[Giovanni],
A flexible FPGA implementation for illuminance-reflectance video enhancement,
RealTimeIP(8), No. 1, March 2013, pp. 81-93.
WWW Link. 1303
BibRef

Kumaki, T.[Takeshi], Kono, Y.[Yutaka], Ishizaki, M.[Masakatsu], Koide, T.[Tetsushi], Mattausch, H.J.[Hans Jürgen],
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory,
IEICE(E90-D), No. 1, January 2007, pp. 346-354.
DOI Link 0701
BibRef

Chandrasekaran, S.[Shrutisagar], Amira, A.[Abbes], Shi, M.H.[Ming-Hua], Bermak, A.[Amine],
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Sriram, V.[Vinay], Kearney, D.[David],
Multiple parallel FPGA implementations of a Kolmogorov phase screen generator,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Chaikalis, D.P., Sgouros, N.P., Maroulis, D.E.,
A real-time FPGA architecture for 3D reconstruction from integral images,
JVCIR(21), No. 1, January 2010, pp. 9-16.
Elsevier DOI 1002
Three-dimensional; Integral image; Image reconstruction; Image representation; Autostereoscopy; Architecture; Real-time; Hardware; FPGA BibRef

Krill, B., Ahmad, A., Amira, A., Rabah, H.,
An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores,
SP:IC(25), No. 5, June 2010, pp. 377-387.
Elsevier DOI 1007
BibRef
And: A1, A3, A2, A4:
A new FPGA-based dynamic partial reconfiguration design flow and environment for image processing applications,
EUVIP10(226-231).
IEEE DOI 1110
Dynamic partial reconfiguration (DPR); Design flow; Field programmable gate array (FPGA); IP cores; Image and signal processing BibRef

Ahmad, A.[Afandi], Amira, A.[Abbes], Nicholl, P.[Paul], Krill, B.[Benjamin],
FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration,
RealTimeIP(8), No. 3, September 2013, pp. 327-340.
Springer DOI 1309
BibRef

Ahmad, A., Amira, A., Guarisco, M., Rabah, H., Berviller, Y.,
Efficient implementation of a 3-D medical imaging compression system using CAVLC,
ICIP10(3773-3776).
IEEE DOI 1009
BibRef

Rahman, A.A.H.A.[Ab Al-Hadi Ab], Prihozhy, A.[Anatoly], Mattavelli, M.[Marco],
Pipeline synthesis and optimization of FPGA-based video processing applications with CAL,
JIVP(2011), No. 1 2011, pp. xx-yy.
DOI Link 1203
BibRef

Genovese, M., Napoli, E.,
FPGA-based architecture for real time segmentation and denoising of HD video,
RealTimeIP(8), No. 4, December 2013, pp. 389-401.
WWW Link. 1312
BibRef

Brost, V.[Vincent], Yang, F.[Fan], Meunier, C.[Charles],
Flexible VLIW processor based on FPGA for efficient embedded real-time image processing,
RealTimeIP(9), No. 1, March 2014, pp. 47-59.
WWW Link. 1403
BibRef

Tomasi, M.[Matteo], Pundlik, S.[Shrinivas], Luo, G.[Gang],
FPGA-DSP co-processing for feature tracking in smart video sensors,
RealTimeIP(11), No. 4, April 2016, pp. 751-767.
WWW Link. 1604
BibRef

Nnolim, U.A.[Uche A.],
FPGA-Based Multiplier-Less Log-Based Hardware Architectures for Hybrid Color Image Enhancement System,
IJIG(17), No. 01, 2017, pp. 1750004.
DOI Link 1703
BibRef

Nnolim, U.A.[Uche A.],
FPGA-Based Hardware Architecture for Fuzzy Homomorphic Enhancement Based on Partial Differential Equations,
IJIG(17), No. 04, 2017, pp. 1750022.
DOI Link 1711
BibRef

Huang, J.J.[Jing-Jin], Zhou, G.Q.[Guo-Qing],
On-Board Detection and Matching of Feature Points,
RS(9), No. 6, 2017, pp. xx-yy.
DOI Link 1706
FPGA-based method. BibRef

Sahlbach, H.[Henning], Thiele, D.[Daniel], Ernst, R.[Rolf],
A system-level FPGA design methodology for video applications with weakly-programmable hardware components,
RealTimeIP(13), No. 2, June 2017, pp. 291-309.
WWW Link. 1708
BibRef

Ohkawa, T.[Takeshi], Yamashina, K.[Kazushi], Kimura, H.[Hitomi], Ootsu, K.[Kanemitsu], Yokota, T.[Takashi],
FPGA Components for Integrating FPGAs into Robot Systems,
IEICE(E101-D), No. 2, February 2018, pp. 363-375.
WWW Link. 1802
BibRef

Rapuano, E.[Emilio], Meoni, G.[Gabriele], Pacini, T.[Tommaso], Dinelli, G.[Gianmarco], Furano, G.[Gianluca], Giuffrida, G.[Gianluca], Fanucci, L.[Luca],
An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study,
RS(13), No. 8, 2021, pp. xx-yy.
DOI Link 2104
BibRef

Li, J.H.[Jia-Hao], Xu, M.[Ming], Xie, Y.Z.[Yi-Zhuang], Chen, H.[He],
Constrained Optimization of FPGA Design for Spaceborne InSAR Processing,
RS(14), No. 19, 2022, pp. xx-yy.
DOI Link 2210
BibRef

Nguyen, V.C.[Van-Cam], Nakashima, Y.[Yasuhiko],
Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform,
IEICE(E106-D), No. 6, June 2023, pp. 1117-1129.
WWW Link. 2306
BibRef

Kawakami, H.[Hiroki], Watanabe, H.[Hirohisa], Sugiura, K.[Keisuke], Matsutani, H.[Hiroki],
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs,
IEICE(E106-D), No. 7, July 2023, pp. 1186-1197.
WWW Link. 2307
BibRef

Fukushima, Y.[Yasuyu], Iizuka, K.[Kensuke], Amano, H.[Hideharu],
Parallel Implementation of CNN on Multi-FPGA Cluster,
IEICE(E106-D), No. 7, July 2023, pp. 1198-1208.
WWW Link. 2307
BibRef

Djomo, A.F.[Alain Fanda], Tiedeu, A.[Alain], Fotsing, J.[Janvier],
Design and implementation in an Altera's cyclone IV EP4CE6E22C8 FPGA board of a fast and robust cipher using combined 1D maps,
IET-IPR(18), No. 7, 2024, pp. 1823-1843.
DOI Link 2405
chaos, chaotic communication, computational complexity, cryptography, hardware description languages, statistical analysis BibRef

Zhou, S.[Shuang], Zhou, L.[Li],
Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm,
RS(16), No. 20, 2024, pp. 3892.
DOI Link 2411
BibRef

Bollengier, T., Najem, M., Le Lann, J.C., Lagadec, L.,
Demo: Overlay architectures for heterogeneous FPGA cluster management,
DASIP16(239-240)
IEEE DOI 1704
fault tolerant computing BibRef

van der Wal, G.[Gooitzen], Zhang, D.[David], Kandaswamy, I.[Indu], Marakowitz, J.[James], Kaighn, K.[Kevin], Zhang, J.[Joe], Chai, S.[Sek],
FPGA acceleration for feature based processing applications,
ECVW15(42-47)
IEEE DOI 1510
Acceleration BibRef

Góngora-Martín, C., Castillo-Atoche, A., Estrada-López, J., Vázquez-Castillo, J., Ortegón-Aguilar, J., Carrasco-Álvarez, R.,
Hybrid FPGA/ARM Co-design for Near Real Time of Remote Sensing Imagery,
CASI14(1039-1046).
Springer DOI 1411
BibRef

Rentería-Cedano, J.A., Aguilar-Lobo, L.M., Ortega-Cisneros, S., Loo-Yau, J.R., Raygoza-Panduro, J.J.[Juan J.],
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems,
CIARP14(88-95).
Springer DOI 1411
BibRef

Eibensteiner, F.[Florian], Kogler, J.[Juergen], Scharinger, J.[Josef],
A High-Performance Hardware Architecture for a Frameless Stereo Vision Algorithm Implemented on a FPGA Platform,
ECVW14(637-644)
IEEE DOI 1409
BibRef

Ladig, R.[Robert], Shimonomura, K.[Kazuhiro],
FPGA-Based Fast Response Image Analysis for Autonomous or Semi-autonomous Indoor Flight,
ECVW14(682-687)
IEEE DOI 1409
Aerial robotics; FPGA; Monocular vision; Onboard vision; Quadrotor BibRef

Bartovsky, J.[Jan], Dokladalova, E.[Eva], Dokladal, P.[Petr], Akil, M.[Mohamed],
Efficient FPGA architecture for oriented 1-D opening and pattern spectrum,
ICIP12(1689-1692).
IEEE DOI 1302
BibRef

Said, Y.[Yahia], Saidani, T.[Taoufik], Smach, F.[Fethi], Atri, M.[Mohamed], Snoussi, H.[Hichem],
Embedded Real-Time Video Processing System on FPGA,
ICISP12(85-92).
Springer DOI 1208
BibRef

Schumann, T.[Thomas], Susanti, A.R.D.[Anita Ratna Dewi],
FPGA design for image processing using a GUI of a web-based VHDL Code Generator,
VCIP11(1).
IEEE DOI 1201
BibRef

Meng, H.Y.[Hong-Ying], Appiah, K.[Kofi], Hunter, A.[Andrew], Dickinson, P.[Patrick],
FPGA implementation of Naive Bayes classifier for visual object recognition,
ECVW11(123-128).
IEEE DOI 1106
BibRef

Park, S.[Sungho], Kestur, S.[Srinidhi], Irick, K.M.[Kevin M.], Narayanan, V.[Vijaykrishnan],
Accelerating neuromorphic vision on FPGAs,
ECVW11(103-108).
IEEE DOI 1106
BibRef

Pedre, S.[Sol], Stoliar, A.[Andres], Borensztejn, P.[Patricia],
Real Time Hot Spot Detection Using FPGA,
CIARP09(595-602).
Springer DOI 0911
BibRef

Wang, W.[Wei], Li, W.[Wei],
Design of Reconfigurable LED Illumination Control System Based on FPGA,
CISP09(1-4).
IEEE DOI 0910
BibRef

Appiah, K.[Kofi], Meng, H.Y.[Hong-Ying], Hunter, A.[Andrew], Dickinson, P.[Patrick],
Binary histogram based split/merge object detection using FPGAs,
ECVW10(45-52).
IEEE DOI 1006
BibRef

Farabet, C.[Clement], Poulet, C.[Cyril], Le Cun, Y.L.[Yann L.],
An FPGA-based stream processor for embedded real-time vision with Convolutional Networks,
EmbedCV09(878-885).
IEEE DOI 0910
BibRef

Hao, Y.Q.[Yong-Qi], Zhang, Y.[Yan], Zhang, L.S.[Lin-Sheng], Liu, L.[Li],
An Automatic Power Estimation Methodology for FPGA-Based Digital Signal Processing Systems,
CISP09(1-4).
IEEE DOI 0910
BibRef

Boudabous, A., Atitallah, A.B.[A. Ben], Kadionik, P., Khriji, L., Masmoudi, N.,
FPGA Codesign Implementation of Vector Directional Filter,
IPTA08(1-5).
IEEE DOI 0811
BibRef

Fresse, V.[Virginie], Tan, J.Y.[Jun-Yan], Rousseau, F.[Frederic],
Exploration of an adaptive NoC architecture on FPGA dedicated to multi and hysperspectral algorithm for art authentication,
IPTA10(529-534).
IEEE DOI 1007
BibRef

Houzet, D.[Dominique], Fresse, V.[Virginie], Konik, H.,
FPGA memory optimization for real-time imaging,
DASIP16(176-182)
IEEE DOI 1704
cache storage BibRef

Tan, J.Y.[Jun-Yan], Zhang, L.L.[Lin-Lin], Fresse, V.[Virginie], Legrand, A.C.[Anne Claire], Houzet, D.[Dominique],
A predictive and parametrized architecture for image analysis algorithm implementations on FPGA adapted to multispectral imaging,
IPTA08(1-8).
IEEE DOI 0811
BibRef

Baumgartner, D.[Daniel], Rossler, P.[Peter], Kubinger, W.[Wilfried],
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms,
EmbedCV07(1-8).
IEEE DOI 0706
BibRef

Cabani, C.[Cristina], MacLean, W.J.[W. James],
A Proposed Pipelined-Architecture for FPGA-Based Affine-Invariant Feature Detectors,
EmbedCV06(121).
IEEE DOI 0609
BibRef

MacLean, W.J.,
An Evaluation of the Suitability of FPGAs for Embedded Vision Systems,
EmbedCV05(III: 131-131).
IEEE DOI 0507
BibRef

Chang, C.J.[Chi-Jeng], Wu, W.T.[Wu-Ting], Su, H.C.[Hui-Ching], Huang, Z.Y.[Zen-Yi], Li, H.Y.[Hsin-Yen],
ARM Based Microcontroller for Image Capturing in FPGA Design,
ISVC05(672-677).
Springer DOI 0512
BibRef

McCurry, P., Morgan, F., Kilmartin, L.,
Xilinx FPGA Implementation of an Image Classifier for Object Detection Applications,
ICIP01(III: 346-349).
IEEE DOI 0108
BibRef

Draper, B.A., Böhm, A.P.W.[A.P. Willem], Hammes, J., Najjar, W., Beveridge, J.R., Ross, C., Chawathe, M., Desai, M., Bins, J.,
Compiling SA-C Programs to FPGAs: Performance Results,
CVS01(220-235).
Springer DOI 0106
BibRef

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