20.2.6.1 Reconfigurable Mesh Architectures and Algorithms

Chapter Contents (Back)
Reconfigurable Mesh. Parallel Algorithms.

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Tsai, H.R.[Horng-Ren], Horng, S.J.[Shi-Jinn], Lee, S.S.[Shung-Shing], Tsar, S.S.[Shun-Shan], Kao, T.W.[Tzong-Wann],
Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System,
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Elsevier DOI 9705

See also Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks. Clustering. BibRef

Tsai, H.R., Horng, S.J.,
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Tsai, H.R.[Horng-Ren], Horng, S.J.[Shi-Jinn], Tsai, S.S.[Shun-Shan], Lee, S.S.[Shung-Shing], Kao, T.W.[Tzong-Wann], Chen, C.H.[Chia-Ho],
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Lee, S.S.[Shung-Shing], Horng, S.J.[Shi-Jinn], Tsai, H.R.[Horng-Ren], Lee, Y.H.[Yu-Hua],
Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks,
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Elsevier DOI 9708

See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. and
See also Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System. BibRef

Lee, S.S.[Shung-Shing], Horng, S.J.[Shi-Jinn], Tsai, H.R.[Horng-Ren],
Entropy Thresholding and Its Parallel Algorithm on the Reconfigurable Array of Processors with Wider Bus Networks,
IP(8), No. 9, September 1999, pp. 1229-1242.
IEEE DOI
See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. BibRef 9909

Wu, C.H.[Chin-Hsiung], Horng, S.J.[Shi-Jinn], Chen, Y.W.[Yi-Wen], Lee, W.Y.[Wei-Yi],
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Constant-Time Thresholding on Reconfigurable Mesh,
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Llamocca, D., Pattichis, M.,
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Reconfigurable Processor for Binary Image Processing,
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Springer DOI 1403
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Springer DOI 1403
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Tai, Y., Hu, W., Guo, L.[Lantian], Mao, B., Mu, D.,
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Li, L.[Lin], Fanni, T., Viitanen, T., Xie, R.J.[Ren-Jie], Palumbo, F., Raffo, L., Huttunen, H., Takala, J., Bhattacharyya, S.S.,
Low power design methodology for signal processing systems using lightweight dataflow techniques,
DASIP16(82-89)
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data flow analysis BibRef

Vranjkovic, V., Struharik, R.,
Coarse-grained reconfigurable hardware accelerator of machine learning classifiers,
WSSIP16(1-5)
IEEE DOI 1608
decision trees BibRef

Amira, A.,
Reconfigurable computing for imaging systems,
IPTA14(1-1)
IEEE DOI 1503
curvelet transforms BibRef

Marques, N., Rabah, H., Dabellani, E., Weber, S.,
Efficient reconfigurable entropy coder for embedded multi-standards video adaptation,
ECVW11(144-149).
IEEE DOI 1106
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Pamula, W.[Wieslaw],
Feature Extraction Using Reconfigurable Hardware,
ICCVG10(II: 158-165).
Springer DOI 1009
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Cumplido, R.[René], Carrasco-Ochoa, J.A.[J. Ariel], Feregrino, C.[Claudia],
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Chai, S.M.[Sek M.], Bellas, N.[Nikolaos], Kujawa, G.[Greg], Ziomek, T.[Tom], Dawson, L.[Linda], Scaminaci, T.[Tony], Dwyer, M.[Malcolm], Linzmeier, D.[Dan],
Reconfigurable Streaming Architectures for Embedded Smart Cameras,
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Flexible Hardware Architecture for 2D Seprable Scaling Using Convolution Interpolation,
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Accelerating svd on reconfigurable hardware for image denoising,
ICIP04(I: 259-262).
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Alfehaid, W.M.[Waleed M.], Khan, A.I.[Asad I.], Amin, A.H.M.[Anang Hudaya Muhamad],
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Benitez, D.[Domingo], Cabrera, J.[Jorge],
Reactive Computer Vision System with Reconfigurable Architecture,
CVS99(348 ff.).
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Bugeja, A.[Alexander], Yang, W.[Woodward],
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Bhandarkar, S.M., Arabnia, H.R.,
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ICPR94(C:240-244).
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Prototyping of interactive satellite image analysis tools using a real-time data-flow computer,
CIAP95(683-688).
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ICIP94(III: 678-680).
IEEE DOI 9411
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Leite, N.J., de Barros, M.A.,
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ICIP94(III: 659-663).
IEEE DOI 9411
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Weil, F.J., Jamieson, L.H., Delp, E.J.,
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ICPR90(II: 318-323).
IEEE DOI 9208
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Samal, A.,
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ICPR90(II: 521-523).
IEEE DOI 9208
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Chianese, A., Cordella, L.P., de Santo, M., Marcelli, A., Vento, M.,
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ICPR88(II: 724-726).
IEEE DOI 8811
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Garda, P., Reichart, A., Rodriguez, H., Devos, F., Zavidovique, B.,
Yet another mesh array smart sensor?,
ICPR88(II: 863-865).
IEEE DOI 8811
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Multi-Processor Algorithms, Pyramid Machines .


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