19.2.6.1 Reconfigurable Mesh Architectures and Algorithms

Chapter Contents (Back)
Reconfigurable Mesh. Parallel Algorithms.

Miller, R., and Stout, Q.F.[Quentin F.],
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Image Computations on Reconfigurable VLSI Arrays,
CVPR88(925-930).
IEEE DOI BibRef 8800

Bondalapati, K., Prasanna, V.K.,
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PIEEE(90), No. 7, July 2002, pp. 1201-1217.
IEEE DOI 0207
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Kasabov, N.K.,
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Shapiro, L.G.[Linda G.], Haralick, R.M.[Robert M.], and Goulish, M.J.[Micheal J.],
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Siegel, H.J., Armstrong, J.B., Watson, D.W.,
Mapping Computer-Vision-Related Tasks onto Reconfigurable Parallel-Processing Systems,
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Olariu, S., Schwing, J.L., Zhang, J.,
Fast Computer Vision Algorithms for Reconfigurable Meshes,
IVC(10), No. 9, November 1992, pp. 610-616.
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Olariu, S., Schwing, J.L., Zhang, J.,
Computing the Hough Transform on Reconfigurable Meshes,
IVC(11), No. 10, December 1993, pp. 623-628.
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Jang, J.W., Park, H., Prasanna, V.K.,
A Fast Algorithm for Computing a Histogram on Reconfigurable Mesh,
PAMI(17), No. 2, February 1995, pp. 97-106.
IEEE DOI BibRef 9502

Haralick, R.M., Somani, A.K., Wittenbrink, C.M., Johnson, R., Cooper, K., Shapiro, L.G., Phillips, I.T., Hwang, J.N., Cheung, W., Yao, Y.H., Chen, C.H., Yang, L., Daughterty, B., Lorbeski, B., Loving, K., Miller, T., Parkins, L., Soos, S.,
Proteus: A Reconfigurable Computational Network for Computer Vision,
MVA(8), No. 2, 1995, pp. 85-100. BibRef 9500
Earlier: ICPR92(IV:43-54).
IEEE DOI BibRef

Kanungo, T., Chiou, G.I., Somani, A.K., Haralick, R.M.,
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Anguita, D.[Davide], di Gesù, V.[Vito], Gerardi, G.[Gaetano], Lenzitti, B.[Biagio], Tegolo, D.[Domenico],
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MVA(8), No. 5, 1995, pp. 343-350.
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Tegolo, D.[Domenico], Lenzitti, B.[Biagio], Isgro, F., di Gesù, V.[Vito],
Dynamic interface for machine vision systems,
ICPR94(C:323-326).
IEEE DOI 9410
BibRef

Tsai, H.R., Horng, S.J., Lee, S.S., Tsai, S.S., Kao, T.W.,
Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System,
PR(30), No. 5, May 1997, pp. 801-815.
WWW Link. 9705
See also Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks. Clustering. BibRef

Tsai, H.R., Horng, S.J.,
Optimal parallel clustering algorithms on a reconfigurable array of processors with wider bus networks,
IVC(17), No. 13, 1 November 1999, pp. 925-936.
WWW Link. 9911
BibRef

Tsai, H.R.[Horng-Ren], Horng, S.J.[Shi-Jinn], Tsai, S.S.[Shun-Shan], Lee, S.S.[Shung-Shing], Kao, T.W.[Tzong-Wann], Chen, C.H.[Chia-Ho],
Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,
CVIU(71), No. 3, September 1998, pp. 393-412.
DOI Link BibRef 9809

Lee, S.S., Horng, S.J., Tsai, H.R., Lee, Y.H.,
Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks,
PR(30), No. 9, September 1997, pp. 1521-1532.
WWW Link. 9708
See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. and See also Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System. BibRef

Lee, S.S., Horng, S.J., Tsai, H.R.,
Entropy Thresholding and Its Parallel Algorithm on the Reconfigurable Array of Processors with Wider Bus Networks,
IP(8), No. 9, September 1999, pp. 1229-1242.
IEEE DOI See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. BibRef 9909

Wu, C.H.[Chin-Hsiung], Horng, S.J.[Shi-Jinn], Chen, Y.W.[Yi-Wen], Lee, W.Y.[Wei-Yi],
Designing scalable and efficient parallel clustering algorithms on arrays with reconfigurable optical buses,
IVC(18), No. 13, October 2000, pp. 1033-1043.
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BibRef

Chung, K.L.[Kuo-Liang],
Constant-Time Thresholding on Reconfigurable Mesh,
RealTimeImg(5), No. 2, April 1999, pp. 77-81. BibRef 9904

Loui, A.C.P., Venetsanopoulos, A.N., Smith, K.C.,
Flexible architectures for morphological image processing and analysis,
CirSysVideo(2), No. 1, March 1992, pp. 72-83.
IEEE Top Reference. 0206
BibRef

Bove, Jr., V.M., Watlington, J.A.,
Cheops: a reconfigurable data-flow system for video processing,
CirSysVideo(5), No. 2, April 1995, pp. 140-149.
IEEE Top Reference. 0206
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Boluda, J.A.[Jose Antonio], Pardo, F.[Fernando],
A reconfigurable architecture for autonomous visual-navigation,
MVA(13), No. 5-6, 2003, pp. 322-331.
HTML Version. 0304
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Dias, T.[Tiago], Roma, N.[Nuno], Sousa, L.[Leonel], Ribeiro, M.[Miguel],
Reconfigurable architectures and processors for real-time video motion estimation,
RealTimeIP(2), No. 4, December 2007, pp. 191-205.
Springer DOI 0712
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Denoulet, J.[Julien], Mérigot, A.[Alain],
An architecture based on reconfigurability and asynchronism for real-time image processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
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Kessal, L.[Lounis], Abel, N.[Nicolas], Karabernou, S.M.[Si Mahmoud], Demigny, D.[Didier],
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Llamocca, D., Pattichis, M.,
A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization,
CirSysVideo(23), No. 3, March 2013, pp. 488-502.
IEEE DOI 1303
BibRef

Zhang, B., Mei, K., Zheng, N.,
Reconfigurable Processor for Binary Image Processing,
CirSysVideo(23), No. 5, May 2013, pp. 823-831.
IEEE DOI 1305
BibRef

Boulos, V.[Vincent], Huet, S.[Sylvain], Fristot, V.[Vincent], Salvo, L.[Luc], Houzet, D.[Dominique],
Efficient implementation of data flow graphs on multi-gpu clusters,
RealTimeIP(9), No. 1, March 2014, pp. 217-232.
Springer DOI 1403
BibRef

Palumbo, F.[Francesca], Carta, N.[Nicola], Pani, D.[Danilo], Meloni, P.[Paolo], Raffo, L.[Luigi],
The multi-dataflow composer tool: Generation of on-the-fly reconfigurable platforms,
RealTimeIP(9), No. 1, March 2014, pp. 233-249.
Springer DOI 1403
BibRef

Bezati, E.[Endri], Thavot, R.[Richard], Roquier, G.[Ghislain], Mattavelli, M.[Marco],
High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms,
RealTimeIP(9), No. 1, March 2014, pp. 251-262.
Springer DOI 1403
BibRef

Wang, X.F.[Xiao-Fang],
Hardware-software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices,
RealTimeIP(9), No. 1, March 2014, pp. 187-204.
WWW Link. 1403
BibRef

Reddy, P.S., Mopuri, S., Acharyya, A.,
A Reconfigurable High Speed Architecture Design for Discrete Hilbert Transform,
SPLetters(21), No. 11, November 2014, pp. 1413-1417.
IEEE DOI 1408
Hilbert transforms BibRef

Cheng, B.[Bo], Guan, X.F.[Xue-Feng], Wu, H.[Huayi], Li, R.[Rui],
Hypergraph+: An Improved Hypergraph-Based Task-Scheduling Algorithm for Massive Spatial Data Processing on Master-Slave Platforms,
IJGI(5), No. 8, 2016, pp. 141.
DOI Link 1609
BibRef


Li, L.[Lin], Fanni, T., Viitanen, T., Xie, R.J.[Ren-Jie], Palumbo, F., Raffo, L., Huttunen, H., Takala, J., Bhattacharyya, S.S.,
Low power design methodology for signal processing systems using lightweight dataflow techniques,
DASIP16(82-89)
IEEE DOI 1704
data flow analysis BibRef

Vranjkovic, V., Struharik, R.,
Coarse-grained reconfigurable hardware accelerator of machine learning classifiers,
WSSIP16(1-5)
IEEE DOI 1608
decision trees BibRef

Amira, A.,
Reconfigurable computing for imaging systems,
IPTA14(1-1)
IEEE DOI 1503
curvelet transforms BibRef

Marques, N., Rabah, H., Dabellani, E., Weber, S.,
Efficient reconfigurable entropy coder for embedded multi-standards video adaptation,
ECVW11(144-149).
IEEE DOI 1106
BibRef

Pamula, W.[Wieslaw],
Feature Extraction Using Reconfigurable Hardware,
ICCVG10(II: 158-165).
Springer DOI 1009
BibRef

Cumplido, R.[René], Carrasco-Ochoa, J.A.[J. Ariel], Feregrino, C.[Claudia],
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification,
CIARP06(665-673).
Springer DOI 0611
BibRef

Chai, S.M.[Sek M.], Bellas, N.[Nikolaos], Kujawa, G.[Greg], Ziomek, T.[Tom], Dawson, L.[Linda], Scaminaci, T.[Tony], Dwyer, M.[Malcolm], Linzmeier, D.[Dan],
Reconfigurable Streaming Architectures for Embedded Smart Cameras,
EmbedCV06(122).
IEEE DOI 0609
BibRef

Arnabat, J., Cardells, F.,
Flexible Hardware Architecture for 2D Seprable Scaling Using Convolution Interpolation,
SIPS05(688-692).
HTML Version. BibRef 0500

Ahmedsaid, A., Amira, A.,
Accelerating svd on reconfigurable hardware for image denoising,
ICIP04(I: 259-262).
IEEE DOI 0505
BibRef

Alfehaid, W.M.[Waleed M.], Khan, A.I.[Asad I.], Amin, A.H.M.[Anang Hudaya Muhamad],
A combined pattern recognition scheme with genetic algorithms for robot guidance using Wireless Sensor Networks,
ICARCV12(759-764).
IEEE DOI 1304
BibRef

Khan, A.I., Mihailescu, P.,
Parallel pattern recognition computations within a wireless sensor network,
ICPR04(I: 777-780).
IEEE DOI 0409
BibRef

Benitez, D.[Domingo], Cabrera, J.[Jorge],
Reactive Computer Vision System with Reconfigurable Architecture,
CVS99(348 ff.).
Springer DOI 0209
BibRef

Bugeja, A.[Alexander], Yang, W.[Woodward],
A Coarse-Grained, Reconfigurable Image Coprocessor,
DARPA97(1389-1392). BibRef 9700

Serra, J.R., Subirana, J.B.[J. Brian],
Adaptive non-cartesian networks for vision,
CIAP97(II: 324-331).
Springer DOI 9709
BibRef

Bhandarkar, S.M., Arabnia, H.R.,
Parallelization of Computer Vision Algorithms on a Reconfigurable Multiprocessor,
ICPR94(C:240-244).
IEEE DOI BibRef 9400

Praud, S.[Stéphane], Germain, P.[Pierre], Plantier, J.[Justin],
Prototyping of interactive satellite image analysis tools using a real-time data-flow computer,
CIAP95(683-688).
Springer DOI 9509
BibRef

Lee, C.W.[Cheol-Whan], Wang, Y.F.[Yuan-Fang], Yang, T.[Tao],
Static global scheduling for optimal computer vision and image processing operations on distributed-memory multiprocessors,
CAIP95(920-925).
Springer DOI 9509
BibRef

Goodenough, J., Shelley, A.J., Seed, N.L.,
HART, a heterogeneous architecture for real-time prototyping, development and implementation of machine vision applications,
ICIP94(III: 678-680).
IEEE DOI 9411
BibRef

Leite, N.J., de Barros, M.A.,
A highly reconfigurable neighborhood image processor based on functional programming,
ICIP94(III: 659-663).
IEEE DOI 9411
BibRef

Weil, F.J., Jamieson, L.H., Delp, E.J.,
Dynamic intelligent scheduling and control of reconfigurable parallel architectures for computer vision/image processing,
ICPR90(II: 318-323).
IEEE DOI 9208
BibRef

Samal, A.,
Design of a dynamically reconfigurable, integrated, parallel vision system,
ICPR90(II: 521-523).
IEEE DOI 9208
BibRef

Chianese, A., Cordella, L.P., de Santo, M., Marcelli, A., Vento, M.,
A preliminary approach to the design and evaluation of a reconfigurable architecture for computer vision,
ICPR88(II: 724-726).
IEEE DOI 8811
BibRef

Garda, P., Reichart, A., Rodriguez, H., Devos, F., Zavidovique, B.,
Yet another mesh array smart sensor?,
ICPR88(II: 863-865).
IEEE DOI 8811
BibRef

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Multi-Processor Algorithms, Pyramid Machines .


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