19.2.10 Pipelined Processors and Algorithms

Chapter Contents (Back)
Parallel Systems. Pipeline Processors.

Gerritsen, F.A., Aardema, L.G.,
Design and use of DIP-1: A fast, flexible and dynamically microprogrammable pipelined image processor,
PR(14), No. 1-6, 1981, pp. 319-330.
Elsevier DOI 0309
BibRef

Carlson, C.R.[Curtis R.], Arbeiter, J.H.[James H.], Bessler, R.F.[Roger F.],
Real-time hierarchal pyramid signal processing apparatus,
US_Patent4,674,125, Jun 16, 1987
WWW Link. BibRef 8706

Bessler, R.F.[Roger F.], Arbeiter, J.H.[James H.], Sinniger, J.O.[Joseph O.],
Multiplexed real-time pyramid signal processing system,
US_Patent4,709,394, Nov 24, 1987
WWW Link. Burt pyramid implementation BibRef 8711

van der Wal, G.S.[Gooitzen S.], Sinniger, J.O.[Joseph O.], Anderson, C.H.[Charles H.],
Implementation architecture for performing hierarchical motion analysis of video images in real time,
US_Patent5,276,513, Jan 4, 1994
WWW Link. BibRef 9401

Andrews, B.A.[Barry A.],
Vector image processing system,
US_Patent4,742,552, May 3, 1988
WWW Link. BibRef 8805

Abbot, L., Haralick, R.M., Zhuang, X.,
Pipeline Architectures for Morphologic Image Analysis,
MVA(1), 1988, pp. 23-40. BibRef 8800

Sanz, J.L.C., and Dinstein, I.,
Projection-Based Geometric Feature Extraction for Computer Vision: Algorithms in Pipeline Architectures,
PAMI(9), No. 1, January 1987, pp. 160-168. Similar to CVPR85 paper. Exploring how the projection can be used for some real computations, and how to do them fast. (There is another paper on projection processing somewhere.) BibRef 8701

Sanz, J.L.C.[Jorge L.C.], Hinkle, E.B.[Eric B.], and Dinstein, I.[Its'hak],
Computing Geometrical Features of Digital Objects in General Purpose Image Processing Pipeline Architectures,
CVPR85(265-270). IBM San Jose. Algorithms designed for current pipeline systems. Shows the results for the computation of the projection of an image. BibRef 8500

Gennery, D.B., and Wilcox, B.,
A Pipelined Processor for Low-Level Vision,
CVPR85(608-613). JPL. System being build for actual processing of data. Basic design is standard. BibRef 8500

Persoon, E.,
A Pipelined Image Analysis System Using Custom Integrated Circuits,
PAMI(10), No. 1, January 1988, pp. 110-116.
IEEE DOI BibRef 8801

Jonker, P.P., Komen, E.R., Kraaijveld, M.A.,
A Scalable, Real-Time, Image-Processing Pipeline,
MVA(8), No. 2, 1995, pp. 110-121. BibRef 9500
Earlier: A1, A2 only: ICPR92(IV:142-146).
IEEE DOI 9208
BibRef

McLauchlan, P.F., Reid, I.D., Fairley, S.M., Murray, D.W.,
The Pipe-Group Architecture Real Time Active Vision,
RealTimeImg(3), No. 5, October 1997, pp. 319-330.
HTML Version. 9712
BibRef

Siyal, M.Y., Fathi, M., Atiquzzaman, M.,
A Parallel Pipeline Based Multiprocessor System for Real-Time Measurement of Road Traffic Parameters,
RealTimeImg(6), No. 3, June 2000, pp. 241-249. 0008
BibRef

Fleury, M., Downton, A.C., Clark, A.F.,
Pipelined parallelisation of automatic face inspection,
MVA(12), No. 4, 2000, pp. 203-211.
Springer DOI 0101
BibRef

Wu, C.W.,
Bit-level pipelined 2-D digital filters for real-time image processing,
CirSysVideo(1), No. 1, March 1991, pp. 22-34.
IEEE Top Reference. 0206
BibRef

Lu, T., Azimi-Sadjadi, M.R.,
Interleaved pipeline structures for two-dimensional recursive filtering,
CirSysVideo(3), No. 1, February 1993, pp. 87-91.
IEEE Top Reference. 0206
BibRef

Gray, III, D.M.[Donald M.], Needle, D.L.[David L.],
Digital signal processor architecture,
US_Patent5,752,073, May 12, 1998
WWW Link. BibRef 9805

Singh, S.[Sameer], Singh, M.[Maneesha],
On the optimality of image processing pipeline,
PR(37), No. 4, April 2004, pp. 707-724.
Elsevier DOI 0403
BibRef

Kumaki, T.[Takeshi], Kuroda, Y.[Yasuto], Ishizaki, M.[Masakatsu], Koide, T.[Tetsushi], Mattausch, H.J.[Hans Jürgen], Noda, H.[Hideyuki], Dosaka, K.[Katsumi], Arimoto, K.[Kazutami], Saito, K.[Kazunori],
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer,
IEICE(E90-D), No. 1, January 2007, pp. 334-345.
DOI Link 0701
BibRef

Seetharaman, G., Venkataramani, B., Lakshminarayanan, G.,
Automation techniques for implementation of hybrid wave-pipelined 2D DWT,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Dokladal, P.[Petr], Dokladalova, E.[Eva],
Computationally efficient, one-pass algorithm for morphological filters,
JVCIR(22), No. 5, July 2011, pp. 411-420.
Elsevier DOI 1106
Mathematical morphology; Serial filters; Nonlinear filters; Real-time implementation; Streaming; Algorithm BibRef

Bartovsky, J.[Jan], Dokladalova, E.[Eva], Dokladal, P.[Petr], Georgiev, V.[Vjaceslav],
Pipeline architecture for compound morphological operators,
ICIP10(3765-3768).
IEEE DOI 1009
BibRef

Acosta, E.[Eric], Liu, A.[Alan],
A pipeline virtual environment architecture for multicore processor systems,
VC(27), No. 11, November 2011, pp. 1099-1114.
WWW Link. 1210
BibRef

Jian, G.A.[Guo-An], Chien, C.A.[Cheng-An], Chen, P.S.[Peng-Sheng], Guo, J.I.[Jiun-In],
A Verification-Aware Design Methodology for Thread Pipelining Parallelization,
IEICE(E95-D), No. 10, October 2012, pp. 2505-2513.
WWW Link. 1210
BibRef

Déforges, O.[Olivier], Normand, N.[Nicolas], Babel, M.[Marie],
Fast recursive grayscale morphology operators: From the algorithm to the pipeline architecture,
RealTimeIP(8), No. 2, June 2013, pp. 143-152.
WWW Link. 1306
BibRef


de Holanda, J.A.M., Cardoso, J.M.P., Marques, E.,
A pipelined multi-softcore approach for the HOG algorithm,
DASIP16(146-153)
IEEE DOI 1704
embedded systems BibRef

Mestiri, H., Kahri, F., Bedoui, M., Bouallegue, B., Machhout, M.,
High throughput pipelined hardware implementation of the KECCAK hash function,
ISIVC16(282-286)
IEEE DOI 1704
Algorithm design and analysis BibRef

Helala, M.A.[Mohamed A.], Qureshi, F.Z.[Faisal Z.],
Accelerating Cost Volume Filtering Using Salient Subvolumes and Robust Occlusion Handling,
ACCV14(II: 316-331).
Springer DOI 1504
pixel labeling. BibRef

Helala, M.A.[Mohamed A.], Pu, K.Q.[Ken Q.], Qureshi, F.Z.[Faisal Z.],
Towards Efficient Feedback Control in Streaming Computer Vision Pipelines,
UCCV14(314-329).
Springer DOI 1504
BibRef
And:
A Stream Algebra for Computer Vision Pipelines,
WebScale14(800-807)
IEEE DOI 1409
Computer Vision Pipelines BibRef

Li, W.W.[Wei-Wei], Li, H.T.[Hai-Tao], Gu, H.[Haiyan],
Study of Remote Sensing Imagery Parallel Segmentation Based on Block and Processing Chain Strategy,
ISIDF11(1-4).
IEEE DOI 1111
BibRef

Ferretti, M., Boffadossi, M.,
A parallel pipelined implementation of LOCO-I for JPEG-LS,
ICPR04(I: 769-772).
IEEE DOI 0409
BibRef

Sawchuk, A.A.,
Optical Signal and Image Processing: From Analog Systems to Digital Pipeline Smart Pixels,
ICIP98(I: 478).
IEEE DOI 9810
BibRef

Kameda, Y., Taoda, T., Minoh, M.,
High Speed 3d Reconstruction by Video Image Pipeline Processing and Division of Spatio-temporal Space,
MVA98(xx-yy). BibRef 9800

Gray, C.T., Liu, W., Hughes, T., Cavin, R., Chen, S.S.,
P3A: a partitionable parallel/pipeline architecture for real-time image processing,
ICPR90(II: 529-531).
IEEE DOI 9208
BibRef

Deguchi, K., Tago, K., Morishita, I.,
Integrated parallel image processings on a pipelined MIMD multi-processor system PSM,
ICPR90(II: 442-444).
IEEE DOI 9208
BibRef

Abdelguerfi, M., Sood, A.K., Khalaf, S.,
Parallel bit-level pipelined VLSI processing unit for the histogramming operation,
CVPR88(945-950).
IEEE DOI 0403
BibRef

Khan, I.,
Implementation of Conditional Processing and Pyramids with a General Purpose Pipelined Pixel Processor,
CVPR86(288-292). Seems to be an enhanced pipeline (2 parallel? processors in it)? BibRef 8600

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Array Processors, Massive Parallel Systems, Pyramids .


Last update:Dec 7, 2017 at 17:23:10