5.5.7.2.6 Architectures and Systems for Matching for Block Coding, Block Motion Estimation

Chapter Contents (Back)
Compression. Block Matching. Compression, Video. Hardware. Architectures. Hardware, real-time implementation and techniques.

Ronsin, J.,
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Tayama, M.[Masashi], Fujiwara, H.[Hiroshi], Maruyama, M.[Masanori],
Motion vector detecting apparatus for video telephone/teleconference systems,
US_Patent5,142,361, Aug 25, 1992
WWW Link. BibRef 9208

Burfield, P.R., Gandini, M., Garino, P., Ghigo, G.C.,
A VLSI implementation study of a 10 Mbit/s video decoder,
SP:IC(5), No. 1-2, February 1993, pp. 59-74.
WWW Link. 0001
VLSI; video codec; block matching; transform coding; digital storage media application BibRef

Jong, H.M.[Her-Ming], Chen, L.G.[Liang-Gee], Chiueh, T.D.[Tzi-Dar],
Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding,
CirSysVideo(4), No. 1, February 1994, pp. 88-90.
IEEE Top Reference. 0206
BibRef

Jong, H.M.[Her-Ming], Chen, L.G.[Liang-Gee], Chiueh, T.D.[Tzi-Dar],
Parallel architectures for 3-step hierarchical search block-matching algorithm,
CirSysVideo(4), No. 4, August 1994, pp. 407-416.
IEEE Top Reference. 0206
BibRef

Chen, M.J.[Mei-Juan], Chen, L.G.[Liang-Gee], Chiueh, T.D.[Tzi-Dar], Lee, Y.P.[Yung-Pin],
A new block-matching criterion for motion estimation and its implementation,
CirSysVideo(5), No. 3, June 1995, pp. 231-236.
IEEE Top Reference. 0206
BibRef

de Vos, L., Schobinger, M.,
VLSI architecture for a flexible block matching processor,
CirSysVideo(5), No. 5, October 1995, pp. 417-428.
IEEE Top Reference. 0206
BibRef

Lee, L.W.[Liang-Wei], Wang, J.F.[Jing-Fa], Lee, J.Y.[Jau-Yien], Shie, J.D.,
Dynamic search-window adjustment and interlaced search for block-matching algorithm,
CirSysVideo(3), No. 1, February 1993, pp. 85-87.
IEEE Top Reference. 0206
BibRef

Dutta, S., Wolf, W.,
A Flexible Parallel Architecture Adapted to Block-Matching Motion-Estimation Algorithms,
CirSysVideo(6), No. 1, February 1996, pp. 74-86.
IEEE Top Reference. BibRef 9602

Baek, Y., Oh, H.S., Lee, H.K.,
An Efficient Block-Matching Criterion for Motion Estimation and Its VLSI Implementation,
Consumer(42), No. 4, November 1996, pp. 885-892. 9701
BibRef

Iwamura, R.[Ryuichi],
Motion vector calculation circuit, with flatness-judgement circuitry, that selects a generated motion vector for output in accordance with a flatness judgement result,
US_Patent5,544,263, Aug 6, 1996
WWW Link. BibRef 9608

Lee, M.S.[Min-Sub],
Method and apparatus for determining true motion vectors for selected pixels,
US_Patent5,581,308, Dec 3, 1996
WWW Link. BibRef 9612
And:
Method and apparatus for encoding/decoding a video signal,
US_Patent5,598,216, Jan 28, 1997
WWW Link. BibRef

Jung, H.M.[Hae-Mook], Lee, M.S.[Min-Sub],
Method and apparatus for encoding a video signal using feature point based motion estimation,
US_Patent5,978,030, Nov 2, 1999
WWW Link. BibRef 9911

Lee, M.S.[Min-Sup],
Method for detecting motion vectors,
US_Patent5,710,603, Jan 20, 1998
WWW Link. BibRef 9801
And:
Method for encoding a video signal using feature point based motion estimation,
US_Patent5,612,743, Mar 18, 1997
WWW Link. BibRef
And: US_Patent5,673,339, Sep 30, 1997
WWW Link. BibRef
And:
Apparatus for encoding a video signal using feature point based motion estimation,
US_Patent5,751,362, May 12, 1998
WWW Link. BibRef
And:
Motion vector estimation method and apparatus for use in an image signal encoding system,
US_Patent5,668,608, Sep 16, 1997
WWW Link. BibRef

Dachiku, K.[Kenshi], Yamaguchi, S.[Shogo], Ozeki, K.[Kazuo], Takahashi, K.[Katsumi], Omokawa, M.[Mitsunori], Kuratate, T.[Takaaki],
Video encoder using global motion estimation and polygonal patch motion estimation,
US_Patent5,592,228, Jan 7, 1997
WWW Link. BibRef 9701

Lin, C.H., Wu, J.L., Tung, Y.S.,
DSRA: A Block Matching Algorithm for Near Real Time Video Encoding,
Consumer(43), No. 2, May 1997, pp. 112-122. 9706
BibRef

Wang, S.W., Wu, J.L., Chuang, S.C., Hsiao, C.C., Tung, Y.S.,
Memory Efficient Hierarchical Lookup Tables for Mass Arbitrary-Side Growing Huffman Trees Decoding,
CirSysVideo(18), No. 10, October 2008, pp. 1335-1346.
IEEE DOI 0811
BibRef

Lin, C.H., Wu, J.L.,
A Lightweight Genetic Block Matching Algorithm for Video Coding,
CirSysVideo(8), No. 4, August 1998, pp. 386-392.
IEEE Top Reference. 9809
BibRef

He, Z.L., Liou, M.L.,
Cost Effective VLSI Architectures for Full Search Block Matching Motion Estimation Algorithm,
VLSIVideo(17), No. 2-3, November 1997, pp. 225-240. 9712
BibRef

He, Z.L., Liou, M.L.,
Design of Fast Motion Estimation Algorithm Based on Hardware Consideration,
CirSysVideo(7), No. 5, October 1997, pp. 819-823.
IEEE Top Reference. 9710
BibRef

He, Z.L., Liou, M.L., Chan, P.C.H., Tsui, C.Y.,
Generic VLSI Architecture for Block Matching Motion Estimation Algorithms,
IJIST(9), No. 4, 1998, pp. 257-273. 9808
BibRef

Lu, J.H., Liou, M.L.,
A Simple And Efficient Search Algorithm for Block-Matching Motion Estimation,
CirSysVideo(7), No. 2, April 1997, pp. 429-433.
IEEE Top Reference. 9704
BibRef

He, Z.L., Liou, M.L.,
A High Performance Fast Search Algorithm for Block Matching Motion Estimation,
CirSysVideo(7), No. 5, October 1997, pp. 826-828.
IEEE Top Reference. 9710
BibRef

Accame, M., de Natale, F.G.B., Giusto, D.D.,
Hierarchical Motion Estimator (HME) for Block-Based Video Coders,
Consumer(43), No. 4, November 1997, pp. 1320-1330. 9801
BibRef

Accame, M., de Natale, F.G.B., Giusto, D.D.,
High-Performance Hierarchical Block-Based Motion Estimation for Real-Time Video Coding,
RealTimeImg(4), No. 1, February 1998, pp. 67-79. 9805
BibRef

Accame, M., de Natale, F.G.B., Desoli, G.S., Giusto, D.D.,
Adaptive 3D interpolation and two-source video coding,
ICIP94(II: 918-922).
IEEE DOI 9411
BibRef

Altunbasak, Y., Tekalp, A.M.,
A Hybrid Video CODEC with Block Based and Mesh Based Motion Compensation Modes,
IJIST(9), No. 4, 1998, pp. 248-256. 9808
BibRef

Vermaut, F., Deville, Y., Marichal, X., Macq, B.,
A distributed adaptive block matching algorithm: Dis-ABMA,
SP:IC(16), No. 5, January 2001, pp. 431-444.
WWW Link. 0201
BibRef

Cheng, S.C., Hang, H.M.,
A Comparison of Block Matching Algorithms Mapped to Systolic Array Implementation,
CirSysVideo(7), No. 5, October 1997, pp. 741-757.
IEEE Top Reference. 9710
BibRef

Nam, S.H., Lee, M.K.,
High-Throughput Block-Matching VLSI Architecture with Low Memory Bandwidth,
CirSysSignal(45), No. 4, April 1998, pp. 508-512. 9805
BibRef

Do, V.L., Yun, K.Y.,
A Low-Power VLSI Architecture for Full-Search Block-Matching Motion Estimation,
CirSysVideo(8), No. 4, August 1998, pp. 393-398.
IEEE Top Reference. 9809
BibRef

Yee, H., Hu, Y.H.[Yu Hen],
A novel modular systolic array architecture for full-search block matching motion estimation,
CirSysVideo(5), No. 5, October 1995, pp. 407-416.
IEEE Top Reference. 0206
BibRef

Yeo, H.G., Hu, Y.H.,
A Modular High Throughput Architecture for Logarithmic Search Block Matching Motion Estimation,
CirSysVideo(8), No. 3, June 1998, pp. 299-315.
IEEE Top Reference. 9806
BibRef

Wang, B.M.[Bor-Min], Yen, J.C.[Jui-Cheng], Chang, S.[Shyang],
Zero waiting-cycle hierarchical block matching algorithm and its array architectures,
CirSysVideo(4), No. 1, February 1994, pp. 18-28.
IEEE Top Reference. 0206
BibRef

Gupta, G., Chakrabarti, C.,
Architectures for hierarchical and other block matching algorithms,
CirSysVideo(5), No. 6, December 1995, pp. 477-489.
IEEE Top Reference. 0206
BibRef

Hsieh, C.H., Lin, T.P.,
VLSI architecture for block-matching motion estimation algorithm,
CirSysVideo(2), No. 2, June 1992, pp. 169-175.
IEEE Top Reference. 0206
BibRef

Tsai, J.C.[Jyi-Chang], Hsieh, C.H.[Chaur-Heh], Weng, S.K.[Shiuh-Ku], Lai, M.F.[Mao-Fu],
Block-matching motion estimation using correlation search algorithm,
SP:IC(13), No. 2, August 1998, pp. 119-133.
WWW Link. BibRef 9808

Song, B.C.[Byung Cheol], Ra, J.B.[Jong Beom],
A fast multi-resolution block matching algorithm for motion estimation,
SP:IC(15), No. 9, July 2000, pp. 799-810.
WWW Link. 0008
See also fast multiresolution feature matching algorithm for exhaustive search in large image databases, A. BibRef

Kim, M.J.[Myung Jun], Lee, Y.G.[Yun Gu], Ra, J.B.[Jong Beom],
A Fast Multi-Resolution Block Matching Algorithm for Multiple-Frame Motion Estimation,
IEICE(E88-D), No. 12, December 2005, pp. 2819-2827.
DOI Link 0512
BibRef

Lee, J.H.[Jae Hun], Lim, K.W.[Kyoung Won], Song, B.C.[Byung Cheol], Ra, J.B.[Jong Beom],
A fast multi-resolution block matching algorithm and its LSI architecture for low bit-rate video coding,
CirSysVideo(11), No. 12, December 2001, pp. 1289-1301.
IEEE Top Reference. 0201
BibRef

Chang, S.[Shifan], Hwang, J.H.[Juin-Haur], Jen, C.W.[Chein-Wei],
Scalable array architecture design for full search block matching,
CirSysVideo(5), No. 4, August 1995, pp. 332-343.
IEEE Top Reference. 0206
BibRef

Tuan, J.C.[Jen-Chieh], Chang, T.S.[Tian-Sheuan], Jen, C.W.[Chein-Wei],
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture,
CirSysVideo(12), No. 1, January 2002, pp. 61-72.
IEEE Top Reference. 0202
BibRef

Kawahito, S., Handoko, D., Tadokoro, Y., Matsuzawa, A.,
Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor,
CirSysVideo(12), No. 12, December 2002, pp. 1084-1092.
IEEE Top Reference. 0301
BibRef

Roma, N.[Nuno], Sousa, L.[Leonel],
Efficient and configurable full-search block-matching processors,
CirSysVideo(12), No. 12, December 2002, pp. 1160-1167.
IEEE Top Reference. 0301
BibRef

Roma, N., Sousa, L.,
Least squares motion estimation algorithm in the compressed DCT domain for H.26x / MPEG-X video sequences,
AVSBS05(576-581).
IEEE DOI 0602
BibRef

Song, B.C., Chun, K.W.,
Multi-Resolution Block Matching Algorithm and Its VLSI Architecture for Fast Motion Estimation in an MPEG-2 Video Encoder,
CirSysVideo(14), No. 9, September 2004, pp. 1119-1137.
IEEE Abstract. 0409
BibRef

Song, B.C., Lee, Y.G., Kim, N.H.,
Block Adaptive Inter-Color Compensation Algorithm for RGB 4:4:4 Video Coding,
CirSysVideo(18), No. 10, October 2008, pp. 1447-1451.
IEEE DOI 0811
BibRef

Cho, J., Jeong, S.C., Lee, D.B., Song, B.C.,
Block Adaptive Interpolation Filter Using Trained Dictionary for Sub-Pixel Motion Compensation,
CirSysVideo(22), No. 2, February 2012, pp. 241-248.
IEEE DOI 1202
BibRef

Lee, Y.G., Song, B.C.,
An Intra-Frame Rate Control Algorithm for Ultralow Delay H.264/Advanced Video Coding (AVC),
CirSysVideo(19), No. 5, May 2009, pp. 747-752.
IEEE DOI 0906
BibRef

Huang, Y.W., Chien, S.Y., Hsieh, B.Y., Chen, L.G.,
Global Elimination Algorithm and Architecture Design for Fast Block Matching Motion Estimation,
CirSysVideo(14), No. 6, June 2004, pp. 898-907.
IEEE Abstract. 0407
BibRef

Huang, S.Y.[Shih-Yu],
Content-aware full search scheme for motion estimation,
IJIST(14), No. 6, 2004, pp. 246-252.
DOI Link 0412
BibRef

Huang, S.Y.[Shih-Yu], Tsai, W.C.[Wei-Chang],
A simple and efficient block motion estimation algorithm based on full-search array architecture,
SP:IC(19), No. 10, December 2004, pp. 975-992.
WWW Link. 0501
BibRef

Huang, S.Y.[Shih-Yu], Cho, C.Y.[Chuan-Yu], Wang, J.S.[Jia-Shung],
Adaptive fast block-matching algorithm by switching search patterns for sequences with wide-range motion content,
CirSysVideo(15), No. 11, November 2005, pp. 1373-1384.
IEEE DOI 0512
BibRef

Peters, H., Sethuraman, R., Beric, A., Meuwissen, P., Balakrishnan, S., Alba Pinto, C.A., Kruijtzer, W., Ernst, F., Alkadi, G., van Meerbergen, J., de Haan, G.,
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications,
CirSysVideo(15), No. 4, April 2005, pp. 508-527.
IEEE Abstract. 0501
BibRef

Babionitakis, K.[Konstantinos], Doumenis, G.A.[Gregory A.], Georgakarakos, G.[George], Lentaris, G.[George], Nakos, K.[Kostantinos], Reisis, D.[Dionysios], Sifnaios, I.[Ioannis], Vlassopoulos, N.[Nikolaos],
A real-time motion estimation FPGA architecture,
RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
Springer DOI 0804
BibRef

Lee, S.S.[Seong-Soo], Hong, M.C.[Min-Cheol], Wee, J.K.[Jae-Kyung],
Low-Hardware-Cost Motion Estimation with Large Search Range for VLSI Multimedia Processors,
IEICE(E88-D), No. 9, September 2005, pp. 2177-2182.
DOI Link 0509
BibRef

Yin, H., Jia, H., Qi, H., Ji, X., Xie, X., Gao, W.,
A Hardware-Efficient Multi-Resolution Block Matching Algorithm and its VLSI Architecture for High Definition MPEG-Like Video Encoders,
CirSysVideo(20), No. 9, September 2010, pp. 1242-1254.
IEEE DOI 1003
BibRef

Ghosh, K.[Kausik], Dhar, A.S.[Anindya Sundar],
A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation,
RealTimeIP(11), No. 1, January 2016, pp. 37-46.
WWW Link. 1601
BibRef
And: Erratum: RealTimeIP(11), No. 1, January 2016, pp. 47.
WWW Link. 1601
BibRef


Batta, K.N.S.[Kota Naga Srinivasarao], Chakrabarti, I.[Indrajit],
A Parallel Architecture for Successive Elimination Block Matching Algorithm,
ICCVGIP08(226-231).
IEEE DOI 0812
BibRef

Porto, M.[Marcelo], Agostini, L.[Luciano], Rosa, L.[Leandro], Susin, A.[Altamiro], Bampi, S.[Sergio],
High Throughput Hardware Architecture for Motion Estimation with 4:1 Pel Subsampling Targeting Digital Television Applications,
PSIVT07(36-47).
Springer DOI 0712
BibRef

Jindal, M., Rao, G.N.,
Adaptive block sub-sampling algorithm for motion-estimation on SIMD processors,
ICIP04(III: 1457-1460).
IEEE DOI 0505
BibRef

Kroupis, N., Dasigenis, M., Argyriou, A.[Antonios], Tatas, K., Soudris, D., Thanailakis, A., Zervas, N.D., Goutis, C.E.,
Power, Performance and Area Exploration of Block Matching Algorithms Mapped on Programmable Processors,
ICIP01(III: 728-731).
IEEE DOI 0108
BibRef

Lai, Y.K., Chen, L.G., Tsai, T.H., and Wu, P.C.,
A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation,
ICIP97(II: 144-147).
IEEE DOI BibRef 9700

Chen, M.C.[Michael C.], Willson, Jr., A.N.[Alan N.],
Design and Optimization of a Differentially Coded Variable Block Size Motion Compensation System,
ICIP96(III: 259-262).
IEEE DOI BibRef 9600

Chapter on Image Processing, Restoration, Enhancement, Filters, Image and Video Coding continues in
Computation and Matching for Region Coding .


Last update:Sep 25, 2017 at 16:36:46