19.2.7 Multi-Processor Algorithms, Cellular, Systolic

Gerritsen, F.A., Verbeek, P.W.,
Implementation of Cellular-Logic Operators Using 3X3 Convolution and Table Lookup Hardware,
CVGIP(27), No. 1, July 1984, pp. 115-123.
WWW Version. BibRef 8407

Guerra, C.,
Systolic Algorithms for Local Operations on Images,
TC(35), 1986, pp. 73-77. BibRef 8600

Pries, W., Thanailakis, A., Card, H.C.,
Group Properties of Cellular Automata and VLSI Applications,
TC(35), 1986, pp. 1013-1024. BibRef 8600

Ibarra, O.H., Kim, S.M., Palis, M.A.,
Designing Systolic Algorithms Using Sequential Machines,
TC(35), 1986, pp. 531-542. BibRef 8600

Ersoy, O.,
Semisystolic Array Implementation of Circular, Skew Circular, and Linear Convolutions,
TC(34), 1985, pp. 190-196. BibRef 8500

Lang, H.W., Schimmler, M., Schmeck, H., Schroder, H.,
Systolic Sorting on a Mesh-Connected Network,
TC(34), 1985, pp. 652-658. BibRef 8500

Groen, F.C.A., Foster, N.J.,
A Fast Algorithm for Cellular Logic Operations on Sequential Machines,
PRL(2), 1984, pp. 333-338. BibRef 8400

Lee, S., Kim, J.H., Groen, F.C.A.,
A fast computational method for minimum square error transform,
ICPR88(I: 392-394).
IEEE DOI may work or IEEE-CS DOI may work. 8811 BibRef

Pecht, J.,
Speeding-up Successive Minkowski Operations with Bit-Plane Computers,
PRL(3), 1985, pp. 113-117. BibRef 8500

Annaratone, M., Arnould, E., Gross, T., Kung, H.T., Lam, M., Menzilcioglu, O., and Webb, J.A.,
The Warp Computer: Architecture, Implementation and Performance,
TC(36), No. 12, December 1987, pp. 1523-1538. BibRef 8712

Shih, Z.C.[Zen-Cheung], Chen, G.H.[Gen-Huey], Lee, R.C.T.,
Systolic Algorithms to Examine All Pairs of Elements,
CACM(30), No. 2, February 1987, pp. 161-167. BibRef 8702

Krithivasan, K., Mahajan, M.,
Systolic Pyramid Automata, Cellular Automata and Array Languages,
PRAI(3), 1989, pp. 405-433. BibRef 8900

Comon, P., Robert, Y., Trystram, D.,
Systolic implementation of the adaptive solution to normal equations,
CVGIP(52), No. 3, December 1990, pp. 402-408.
WWW Version. 0501 BibRef

Crisman, J.D., and Webb, J.A.,
The Warp Machine on Navlab,
PAMI(13), No. 5, May 1991, pp. 451-465.
IEEE Abstract. IEEE Top Reference.
WWW Version. BibRef 9105

de Saint Pierre, T., and Milgram, M.,
New and Efficient Cellular Algorithms for Image Processing,
CVGIP(55), No. 3, May 1992, pp. 261-274.
WWW Version. BibRef 9205

Serot, J., Quenot, G., Zavidovique, B.,
Functional Programming on a Data Flow Architecture: Applications In Real-Time Image Processing,
MVA(7), 1993, pp. 44-56. BibRef 9300

Allart, E., Zavidovique, B.,
Functional computer for low level image processing,
ICPR88(II: 830-832).
IEEE DOI may work or IEEE-CS DOI may work. 8811 BibRef

Wen, K.A., Su, J.Y., Lu, C.Y.,
VLSI Design of Digital Cellular Neural Networks for Image Processing,
JVCIR(5), 1994, pp. 117-126. BibRef 9400

Duff, M.J.B., Fountain, T.J.,
Algorithm design for image processing in the context of cellular logic,
IVC(12), No. 2, March 1994, pp. 80-94.
WWW Version. 0401 BibRef

Duff, M.J.B., Fountain, T.J.,
Enhancing the two-dimensional mesh,
ICPR90(II: 654-659).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Karafyllidis, I., Andreadis, I., Tzionas, P., Tsalides, P., Thanailakis, A.,
A Cellular-Automaton for the Determination of the Mean Velocity of Moving-Objects and Its VLSI Implementation,
PR(29), No. 4, April 1996, pp. 689-699.
WWW Version. BibRef 9604

Andreadis, I., Karafyllidis, I., Tzionas, P., Thanailakis, A., Tsalides, P.,
A New Hardware Module for Automated Visual Inspection Based on a Cellular-Automaton Architecture,
JIRS(16), No. 1, May 1996, pp. 89-102. 9608 BibRef

Kaufman, H.J., Sid-Ahmed, M.A.,
Hardware realization of a 2D IIR semisystolic filter with application to real-time homomorphic filtering,
CirSysVideo(3), No. 1, February 1993, pp. 2-14.
IEEE Top Reference. 0206 BibRef

Sid-Ahmed, M.A.,
A hardware structure for the automatic selection of multi-level thresholds in digital images,
PR(25), No. 12, December 1992, pp. 1517-1528.
WWW Version. 0401 BibRef

Sunder, S., Ramachandran, V.,
Systolic implementation of multidimensional nonrecursive digital filters,
CirSysVideo(3), No. 6, December 1993, pp. 399-407.
IEEE Top Reference. 0206 BibRef

Iyengar, G., Panchanathan, S.,
Systolic array architecture for Gabor decomposition,
CirSysVideo(5), No. 4, August 1995, pp. 355-359.
IEEE Top Reference. 0206 Gabor. BibRef

Shapiro, J.M., Staelin, D.H.,
Algorithms and systolic architectures for multidimensional adaptive filtering via McClellan transformations,
CirSysVideo(2), No. 1, March 1992, pp. 60-71.
IEEE Top Reference. 0206 BibRef

Tzionas, P.[Panagiotis],
A Cellular Automaton Processor for Line and Corner Detection in Gray-Scale Images,
RealTimeImg(6), No. 6, December 2000, pp. 461-470. 0101 BibRef

Karafyllidis, I., Ioannidis, A., Thanailakis, A., Tsalides, P.,
Geometrical Shape-Recognition Using a Cellular Automaton Architecture and Its VLSI Implementation,
RealTimeImg(3), No. 4, August 1997, pp. 243-254. 9710 BibRef

Morita, K., Ueno, S., Imai, K.,
Characterizing the Ability of Parallel Array Generators on Reversible Partitioned Cellular Automata,
PRAI(13), No. 4, June 1999, pp. 523. 0005 BibRef

Reynaga, R.[Rene], Amthauer, E.[Eligio],
Two-dimensional cellular automata of radius one for density classification task,
PRL(24), No. 15, November 2003, pp. 2849-2856.
WWW Version. 0308 BibRef

Mertoguno, S., Bourbakis, N.G.,
A digital retina-like low-level vision processor,
SMC-B(33), No. 5, October 2003, pp. 782-788.
IEEE Abstract. IEEE Top Reference. 0310 BibRef

Torres-Huitzil, C.[Cesar], Arias-Estrada, M.[Miguel],
Real-time image processing with a compact FPGA-based systolic architecture,
RealTimeImg(10), No. 3, June 2004, pp. 177-187.
WWW Version. 0410 BibRef

Torres-Huitzil, C.[César], Arias-Estrada, M.[Miguel],
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing,
JASP(2005), No. 7, 2005, pp. 1024-1034.
WWW Version. 0603 BibRef

Rosin, P.L.[Paul L.],
Training Cellular Automata for Image Processing,
IP(15), No. 7, July 2006, pp. 2076-2087.
IEEE DOI may work or IEEE-CS DOI may work. 0606 BibRef
Earlier: SCIA05(195-204).
WWW Version. 0506 BibRef

Ho, T.Y.[Tze-Yui], Lam, P.M.[Ping-Man], Leung, C.S.[Chi-Sing],
Parallelization of cellular neural networks on GPU,
PR(41), No. 8, August 2008, pp. 2684-2692.
WWW Version. 0805Cellular neural networks; SIMD; GPU BibRef

Kolesnik, M.[Marina], Barlit, A.[Alexander],
Iterative Orientation Tuning in V1: A Simple Cell Circuit with Cross-Orientation Suppression,
SCIA03(232-238).
WWW Version. 0310 BibRef

Stichling, D., Kleinjohann, B.,
CV-SDF -a model for real-time computer vision applications,
WACV02(325-329).
IEEE Abstract. IEEE Top Reference. 0303Synchronous Data Flow model for vision. BibRef

Keil, M.S., Cristobal, G., Neumann, H.,
A neurodynamical retinal network based on reaction-diffusion systems,
CIAP01(209-214).
IEEE Top Reference. 0210 BibRef

Ferretti, M., Rizzo, D.,
On the Synthesis of a Controller for Handling Borders in Systolic Architectures for 1-d Discrete Wavelet Transform,
MVA98(xx-yy). BibRef 9800

Melchert, W.,
Automatic flow control planning for real-time image processing devices,
ICIP96(III: 643-646).
IEEE DOI may work or IEEE-CS DOI may work. 9610 BibRef

Fejes, S., Vajda, F.,
A data-driven algorithm and systolic architecture for image morphology,
ICIP94(II: 550-554).
IEEE DOI may work or IEEE-CS DOI may work. 9411 BibRef

Feng, Z.[Zhaozhi], Huang, Z.[Zailu], Chen, D.W.[Dao-Wen], Wan, F.[Faguan],
Systolic neural network architecture for second order hidden Markov models,
ICPR92(IV:186-189).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Gunzinger, A., Mathis, S., Guggenbuhl, W.,
The synchronous dataflow machine: a computer architecture for real time image processing,
ICPR90(II: 436-441).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Tyagi, A., Bayoumi, M.,
Systolic array implementation of image segmentation by a directed split and merge procedure,
ICPR90(II: 491-493).
IEEE DOI may work or IEEE-CS DOI may work. 9208 BibRef

Giordano, A., Maresca, M., Sandini, B., Vernazza, T., and Ferrari, D.,
A Systolic Convolver for Parallel, Multiresolution Edge Detection,
CVPR85(628-632). (Univ. of Genoa and ELSAG Electronica) Why different from Kung's work? BibRef 8500

Bono, C.M.[Claire M.], Webb, J.A.[Jon A.],
Object Recognition on a Systolic Array,
CMU-RI-TR-87-21, September 1987. BibRef 8709

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Hardware, VLSI Implementations, Processors, Sensor Processing .