19.2.1 Systems and Architectures for Image Processing

Chapter Contents (Back)
Hardware. Architectures.

Unger, S.H.,
A Computer Oriented toward Spatial Problems,
PIRE(46), 1958, pp. 1744-1750. BibRef 5800

McCormick, B.H.,
The Illinois Pattern Recognition Computer ILLIAC III,
TC(12), December 1963, pp. 791-813. BibRef 6312

Russell, J.K.,
A Visual Image Processor,
TC(17), No. 7, July 1968, pp. 635. BibRef 6807

Marks, P.[Philip],
Low-level vision using an array processor,
CGIP(14), No. 3, November 1980, pp. 281-292.
WWW Link. 0501
BibRef

Duff, M.J.B., and Levialdi, S.,
Languages and Architectures for Image Processing,
Academic Press1981. BibRef 8100

Siegel, H.J., Siegel, L.J., Kemmerer, F.C., Muller, P.T., Smalley, H.E., Smith, D.,
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition,
TC(30), 1981, pp. 934-947. BibRef 8100

Dreher, C.T., Parrish, Jr., E.A.,
A potential discrete analog processor for pattern recognition,
PR(13), No. 3, 1981, pp. 207-218.
WWW Link. 0309
BibRef

Shippey, G.A., Bayley, R.J.H., Farrow, A.S.J., Rutovitz, D.R., Tucker, J.H.,
A fast interval processor,
PR(14), No. 1-6, 1981, pp. 345-356.
WWW Link. 0309
BibRef

Ullmann, J.R.,
Video-rate digital image analysis equipment,
PR(14), No. 1-6, 1981, pp. 305-318.
WWW Link. 0309
BibRef

Hwang, K., (Ed.),
Computer Architectures for Image Processing,
Computer(16), No. 1, January 1983, pp. 10-13. BibRef 8301

Sternberg, S.R.[Stanley R.],
Biomedical Image Processing,
Computer(16), No. 1, January 1983, pp. 22-34. The Cyto-computer for morphological operations. BibRef 8301

Preston, Jr., K.[Kendall],
Cellular Logic Computers for Pattern Recognition,
Computer(16), No. 1, January 1983, pp. 36-47. BibRef 8301

Preston, Jr., K.[Kendall],
Some Notes on Cellular Logic Operators,
PAMI(3), No. 4, July 1981, pp. 476-481. BibRef 8107

Preston, Jr., K.[Kendall],
Gray Level Image Processing by Cellular Logic Transforms,
PAMI(5), No. 1, January 1983, pp. 55-58. BibRef 8301

Preston, Jr., K.[Kendall],
Multidimensional Logical Transforms,
PAMI(5), No. 5, September 1983, pp. 539-554. BibRef 8309

Preston, Jr., K.[Kendall], and Norgren, P.E.,
Interactive Image Processor Speeds Pattern Recognition by Computer,
Electronics(45), 23 October 1972, pp. 89-98. BibRef 7210

Potter, J.L.,
Image Processing on the Massively Parallel Processor,
Computer(16), No. 1, January 1983, pp. 62-67. Leading to real-time interaction with the scene. BibRef 8301

Kidode, M.[Masatsugu],
Image Processing Machines in Japan,
Computer(16), No. 1, January 1983, pp. 68-80. BibRef 8301

Parrish, Jr., E.A., Anyiwo, A.O., Batchman, T.E.,
Integrated Optical Processors in Pattern Recognition,
PR(18), No. 3-4, 1985, pp. 227-240.
WWW Link. BibRef 8500

Mitra, S.K., Mondal, K., (Eds.)
Special Issue on Hardware and Software for Digital Signal Processing,
PIEEE(75), No. 9, September 1987, pp. 1139-1332. BibRef 8709

Tewari, N., Wagh, M.D.,
Bit-Sequential Array for Pattern Matching,
PIEEE(74), 1986, pp. 1465-1466. BibRef 8600

Beg, M.R.[Mirza R.], Perl, J.[Julius],
Image processing-system,
US_Patent4,606,065, Aug 12, 1986
WWW Link. BibRef 8608

Hata, S.[Seiji], Horino, H.[Hiroshi], Miyakawa, A.[Akira],
Programmable image processor,
US_Patent4,606,066, Aug 12, 1986
WWW Link. BibRef 8608

Choudhary, A.[Alok], Ranka, S.[Sanjay],
Special Issue Parallel Processing,
Computer(25), No. 2, February 1992. Special issue on parallel processing for computer vision and image understanding. Includes papers on Rochester checker player, Adapt, connection maching and matching, plus a number of project overviews. BibRef 9202

Sanz, J.L.C.,
Special Issue I,
PAMI(10), No. 1, January 1988. Special issue on industrial machine vision and computer vision technology. The issue includes hardware descriptions and applications. Papers distributed throughout the listing. BibRef 8801

Sanz, J.L.C.,
Special Issue II,
PAMI(10), No. 3, May 1988. Special issue on industrial machine vision and computer vision technology II. The issue includes hardware descriptions and applications. Papers are elsewhere. BibRef 8805

Dyer, C.R., (Ed.)
Special Section on Computer Architectures,
PAMI(11), No. 3, March 1989, pp. 225-226.
IEEE Top Reference. Parallel algorithms. BibRef 8903

Cantoni, V.[Virginio], and Levialdi, S.[Stefano],
Matching the Task to an Image Processing Architecture,
CVGIP(22), No. 2, May 1983, pp. 301-309.
WWW Link. BibRef 8305

Cantoni, V.[Virginio], and Levialdi, S.[Stefano],
Multiprocessor Computing for Images,
PIEEE(76), No. 8, August 1988, pp. 959-969. BibRef 8808
And:
PAPIA: A Case History,
PCV88(3-13). BibRef

Levialdi, S.,
Computer architectures for image analysis,
ICPR88(II: 1148-1158).
IEEE DOI BibRef 8800

Ruetz, P.A., Brodersen, R.W.,
An Image-Recognition System Using Algorithmically Dedicated Integrated Circuits,
MVA(1), 1988, pp. 3-22. BibRef 8800

Wallace, R.S., and Howard, M.D.,
HBA Vision Architecture: Built and Benchmarked,
PAMI(11), No. 3, March 1989, pp. 227-232.
IEEE DOI BibRef 8903

Li, H.W.[Hung-Wen], and Maresca, M.[Massimo],
Polymorphic-Torus Architecture for Computer Vision,
PAMI(11), No. 3, March 1989, pp. 233-243.
IEEE DOI Used for component labeling. BibRef 8903

Maresca, M., Li, H., Sheng, M.M.C.,
Parallel Computer Vision on Polymorphic Torus Architecture,
MVA(2), No. 4, 1989, pp. 215-230. BibRef 8900

Duller, A.W.G., Storer, R.H., Thomson, A.R., Dagless, E.L.,
An Associative Processor Array for Image Processing,
IVC(7), No. 2, May 1989, pp. 151-158.
WWW Link. BibRef 8905

Duller, A.W.G., Storer, R.H., Thomson, A.R., Pout, M.R., Dagless, E.L.,
A heterogeneous vision architecture,
ECCV90(576-578).
Springer DOI 9004
BibRef

Weems, Jr., C.C.,
Architectural Requirements of Image Understanding with Respect to Parallel Processing,
PIEEE(79), No. 4, 1991, pp. 537-547. BibRef 9100

Schalkoff, R.J.[Robert J], Nag, H.[Harish],
Decomposition and Parallel Architecture for the Geometric Transformation of Digital Images,
IVC(9), No. 5, October 1991, pp. 275-284.
WWW Link. BibRef 9110

Wechsler, H.,
An Overview of Parallel Hardware Architectures for Computer Vision,
PRAI(6), 1992, pp. 629-649. BibRef 9200

Wyatt, Jr., J.L., Keast, C., Seidel, M., Standley, D., Horn, B.K.P., Knight, T., Sodini, C., Lee, H.S., and Poggio, T.,
Analog VLSI Systems for Image Acquisition and Fast Early Vision Processing,
IJCV(8), No. 3, 1992, pp. 217-230.
Springer DOI BibRef 9200

Huang, K.S., Kuznia, C.B., Jenkins, B.K., Sawchuk, A.A.,
Parallel Architectures for Digital Optical Cellular Image Processing,
PIEEE(82), 1994, pp. 1711-1723. BibRef 9400

Casasent, D.,
General-Purpose Optical Pattern Recognition Image Processors,
PIEEE(82), 1994, pp. 1724-1734. BibRef 9400

Baglietto, P., Maresca, M., Migliardi, M., Zingirian, N.,
Image-Processing on High-Performance RISC Systems,
PIEEE(84), No. 7, July 1996, pp. 917-930. 9607
BibRef

Zingirian, N., Maresca, M.,
On the efficiency of image and video processing programs on instruction level parallel processors,
PIEEE(90), No. 7, July 2002, pp. 1230-1243.
IEEE DOI 0207
BibRef

Alexander, W.E., Reeves, D.S., Gloster, Jr., C.S.,
Parallel Image-Processing with the Block Data-Parallel Architecture,
PIEEE(84), No. 7, July 1996, pp. 947-968. 9607
BibRef
And: IBMRD(44), No. 5, September 2000, pp. 681-702. BibRef

Krikelis, A., Lea, R.M.,
A Modular Massively-Parallel Computing Approach to Image-Related Processing,
PIEEE(84), No. 7, July 1996, pp. 988-1004. 9607
BibRef

Tambouratzis, G., Krikelis, A.,
Implementing the Abingdon Cross benchmark on the ASP,
ICPR92(IV:91-94).
IEEE DOI 9208
BibRef

Hammerstrom, D.W., Lulich, D.P.,
Image Processing Using One-Dimensional Processes Arrays,
PIEEE(84), No. 7, July 1996, pp. 1005-1018. 9607
BibRef

Colaitis, M.J., Jumpertz, J.L., Guerin, B., Cheron, B., Battini, F., Delescure, B., Gautier, E., Geffroy, J.P.,
The Implementation of Pi-I-3, A Parallel Architecture for Video Real-Time Processing: A Case-Study,
PIEEE(84), No. 7, July 1996, pp. 1019-1037. 9607
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Sarpeshkar, R., Kramer, J., Indiveri, G., Koch, C.,
Analog VLSI Architectures for Motion Processing: From Fundamental Limits to System Applications,
PIEEE(84), No. 7, July 1996, pp. 969-987. 9607
BibRef

Wittenbrink, C.M., Somani, A.K.,
Cache Tiling for High Performance Morphological Image Processing,
MVA(7), 1993, pp. 12-22. BibRef 9300

Wittenbrink, C.M., Somani, A.K., Chen, C.H.,
Cache Write Generate for Parallel Image-Processing on Shared-Memory Architectures,
IP(5), No. 7, July 1996, pp. 1204-1208.
IEEE DOI 9607
BibRef

Houzet, D.,
Real-Time Image-Processing with a MIMD Computer,
RealTimeImg(2), No. 6, December 1996, pp. 383-392. 9702
BibRef

Ranganathan, N., (Guest ed.),
Special Issue: VLSI and Parallel Computing for Pattern Recognition and Artificial Intelligence,
PRAI(9), No. 2, April 1995, pp. 173-462. BibRef 9504

Bhandarkar, S.M., Arabnia, H.R., and Smith, J.W.,
A Reconfigurable Architecture for Image Processing and Computer Vision,
PRAI(9), 1995, pp. 201-229. BibRef 9500

Bokka, V., Gurla, H., Olariu, S., Schwing, J.L., and Stojmenovic, I.,
Time-Optimal Digital Geometry Algorithms on Meshes with Multiple Broadcasting,
PRAI(9), 1995, pp. 601-613. BibRef 9500

Ziavras, S.G., and Sideras, M.A.,
Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers,
PRAI(9), 1995, pp. 679-698. BibRef 9500

Ghoshw, I., and Majumdar, B.,
VLSI Implementation of an Efficient ASIC Architecture for Real-Time Rotation of Digital Images,
PRAI(9), 1995, pp. 449-462. BibRef 9500

Park, J.W.,
An Efficient Memory System for Image Processing,
TC(35), 1986, pp. 669-. BibRef 8600

Chellappa, R., Rosenfeld, A.,
Vision Engineering: Designing Computer Vision Systems,
HPRCV97(Chapter V:1). (Univ. Maryland) BibRef 9700

Ranganathan, N., Vijaykrishnan, N., Bhavanishankar, N.,
A Linear Array Processor with Dynamic Frequency Clocking for Image Processing Applications,
CirSysVideo(8), No. 4, August 1998, pp. 435-445.
IEEE Top Reference. 9809
BibRef
Earlier: A1, A3, A2:
A Dynamic Frequency Linear Array Processor for Image Processing,
ICPR96(IV: 611-615).
IEEE DOI 9608
(Univ. of Florida, USA) BibRef

Vijaykrishnan, N., Ranganathan, N., Bhavanishankar, N.,
DFLAP: a dynamic frequency linear array processor,
ICIP96(II: 1007-1010).
IEEE DOI 9610
BibRef

Basoglu, C., Kim, D., Gove, R.J., Kim, Y.,
High-Performance Image Computing With Modern Microprocessors,
IJIST(9), No. 6, 1998, pp. 407-415. 9812
BibRef

Haynes, S.D.[Simon D.], Stone, J.[John], Cheung, P.Y.K.[Peter Y.K.], Luk, W.[Wayne],
Video Image Processing with the Sonic Architecture,
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Fahmy, S.A.[Suhaib A.], Bouganis, C.S.[Christos-Savvas], Cheung, P.Y.K.[Peter Y. K.], Luk, W.[Wayne],
Real-time hardware acceleration of the trace transform,
RealTimeIP(2), No. 4, December 2007, pp. 235-248.
Springer DOI 0712
BibRef

Siegel, M., Nagata, S.,
Just Enough Reality: Comfortable 3-D Viewing via Microstereopsis,
CirSysVideo(10), No. 3, April 2000, pp. 387-396.
IEEE Top Reference. 0004
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Siegel, M.,
'Just Enough Reality,' Microstereopsis and the Prospect of Zoneless Autostereoscopic Displays,
ICIP00(Vol I: 9-12).
IEEE DOI 0008
BibRef

Macq, B.[Benoît], Labeau, F.[Fabrice], Desset, C.[Claude], Vandendorpe, L.[Luc],
Image processing for multimedia terminals and related architectures,
SP(80), No. 7, July 2000, pp. 1167-1183. 0008
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Meribout, M.[Mahmoud], Nakanishi, M.[Mamoru], Ogura, T.[Takeshi],
Accurate and Real-time Image Processing on a New PC-compatible Board,
RealTimeImg(8), No. 1, February 2002, pp. 35-51.
DOI Link 0204
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Meribout, M.[Mahmoud], Khriji, L.[Lazher], Nakanishi, M.[Mamoru],
A robust hardware algorithm for real-time object tracking in video sequences,
RealTimeImg(10), No. 3, June 2004, pp. 145-159.
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Veeravalli, B.[Bharadwaj], Ranganath, S.[Surendra],
Theoretical and experimental study on large size image processing applications using divisible load paradigm on distributed bus networks,
IVC(20), No. 13-14, December 2002, pp. 917-935.
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Dankers, A.[Andrew], Zelinsky, A.[Alexander],
CeDAR: A real-world vision system: Mechanism, control and visual processing,
MVA(16), No. 1, December 2004, pp. 47-58.
Springer DOI 0501
BibRef
Earlier:
A Real-World Vision System: Mechanism, Control, and Vision Processing,
CVS03(223 ff).
Springer DOI 0306
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de Souza, G.N.[Guilherme N.], Kak, A.C.,
A subsumptive, hierarchical, and distributed vision-based architecture for smart robotics,
SMC-B(34), No. 5, October 2004, pp. 1988-2002.
IEEE Abstract.
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BibRef

Witt, S.,
Real-time video effects on a PlayStation2,
VISP(152), No. 4, August 2005, pp. 448-453.
DOI Link 0512
Use the hardware for analysis. BibRef

Budagavi, M.[Madhukar],
Real-time image and video processing in portable and mobile devices,
RealTimeIP(1), No. 1, October 2006, pp. 3-7.
Springer DOI 0001
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Brunelli, C.[Claudio], Garzia, F.[Fabio], Nurmi, J.[Jari],
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RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
Springer DOI 0804
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Braun, L.[Lars], Göhringer, D.[Diana], Perschke, T.[Thomas], Schatz, V.[Volker], Hübner, M.[Michael], Becker, J.[Jürgen],
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture,
RealTimeIP(4), No. 2, June 2009, pp. xx-yy.
Springer DOI 0905
BibRef

Ryan, Ø.[Øyvind],
Runlength-Based Processing Methods for Low Bit-depth Images,
IP(18), No. 9, September 2009, pp. 2048-2058.
IEEE DOI 0909
BibRef
Earlier:
The RIM Framework for Image Processing,
ACIVS06(150-160).
Springer DOI 0609
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Zachariah, D., Jansson, M., Bengtsson, M.,
Utilization of Noise-Only Samples in Array Processing With Prior Knowledge,
SPLetters(20), No. 9, 2013, pp. 865-868.
IEEE DOI 1308
array signal processing BibRef

Dhandapani, V.[Vaithiyanathan], Ramachandran, S.[Seshasayanan],
Power-optimized log-based image processing system,
JIVP(2014), No. 1, 2014, pp. 37.
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Mohanty, B.K., Meher, P.K.,
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation,
IET-IPR(8), No. 6, June 2014, pp. 345-353.
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Yazawa, Y.[Yoshifumi], Yoshimi, T.[Tsutomu], Tsuzuki, T.[Teruyasu], Dohi, T.[Tomomi], Yamauchi, Y.[Yuji], Yamashita, T.[Takayoshi], Fujiyoshi, H.[Hironobu],
FPGA Hardware with Target-Reconfigurable Object Detector,
IEICE(E98-D), No. 9, September 2015, pp. 1637-1645.
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Amroui, A.E., Sethom, K.,
A new framework for autonomic mobile cloud computing,
ICCVIA15(1-5)
IEEE DOI 1603
cloud computing BibRef

Eberli, F.[Felix],
Next Generation FPGAs and SOCs: How Embedded Systems Can Profit,
ECVW13(610-613)
IEEE DOI 1309
FPGA; JPEG; Rectification; SGM; Stixel; Zynq; Zynq Module BibRef

Gudis, E.[Eduardo], Lu, P.[Pullan], Berends, D.[David], Kaighn, K.[Kevin], van der Wal, G.[Gooitzen], Buchanan, G.[Gregory], Chai, S.[Sek], Piacentino, M.[Michael],
An Embedded Vision Services Framework for Heterogeneous Accelerators,
ECVW13(598-603)
IEEE DOI 1309
FPGA BibRef

Yogamani, S.K.[Senthil Kumar], Prasad, B.H.P.[B.H. Pawan], Narasimha, R.[Rajesh],
Scalable Frame to Block Based Automatic Converter for Efficient Embedded Vision Processing,
ECVW13(592-597)
IEEE DOI 1309
BibRef

Zaghloul, M.S., Saleh, M.,
Implementation of FPGA for decision making in portable automatic testing systems for IC's library & digital circuits,
AIPR11(1-6).
IEEE DOI 1204
BibRef

Khalvati, F., Tizhoosh, H.R.,
An efficient architecture for hardware implementations of image processing algorithms,
CIIP09(20-26).
IEEE DOI 0903
BibRef

Clienti, C.[Christophe], Bilodeau, M.[Michel], Beucher, S.[Serge],
An Efficient Hardware Architecture without Line Memories for Morphological Image Processing,
ACIVS08(xx-yy).
Springer DOI 0810
BibRef

Kywe, W.W.[Wyne Wyne], Fujiwara, D.[Daisuke], Murakami, K.[Kazuhito],
Scheduling of Image Processing Using Anytime Algorithm for Real-time System,
ICPR06(III: 1095-1098).
IEEE DOI 0609
BibRef

Bariamis, D.G.[Dimitris G.], Iakovidis, D.K.[Dimitris K.], Maroulis, D.E.[Dimitris E.],
Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images,
ACIVS06(67-77).
Springer DOI 0609
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Bariamis, D.G., Iakovidis, D.K., Maroulis, D.E., Karkanis, S.A.,
An FPGA-based architecture for real time image feature extraction,
ICPR04(I: 801-804).
IEEE DOI 0409
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Fung, J., Mann, S.,
Using multiple graphics cards as a general purpose parallel computer: applications to computer vision,
ICPR04(I: 805-808).
IEEE DOI 0409
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Bertamini, F., Brunelli, R., Lanz, O., Roat, A., Santuari, A., Tobia, F., Xu, Q.,
Olympus: An Ambient Intelligence Architecture on the Verge of Reality,
CIAP03(139-144).
IEEE DOI 0310
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Chamizo, J.M.G.[Juan Manuel García], Guilló, A.F.[Andrés Fuster], López, J.A.[Jorge Azorín], Pérez, F.M.[Francisco Maciá],
Architecture for Image Labelling in Real Conditions,
CVS03(131 ff).
Springer DOI 0306
BibRef

Sloman, A.,
Evolvable Biologically Plausible Visual Architectures,
BMVC01(Session 3: Colour & Systems).
HTML Version. The University of Birmingham 0110
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Kyo, S., Koga, T., Okazaki, S.,
IMAP-CE: A 51.2 Gops Video Rate Image Processor with 128 VLIW Processing Elements,
ICIP01(III: 294-297).
IEEE DOI 0108
BibRef

Harley, C.[Cormac],
Storage of Digital Camera Images,
ICIP99(III:940-942).
IEEE DOI BibRef 9900

Sodini, C.G.[Charles G.], Gealow, J.C.[Jeffrey C.], Talib, Z.A.[Zubair A.], Masaki, I.[Ichiro],
Integrated Memory/Logic Architecture for Image Processing,
DARPA98(1215-1220). BibRef 9800

Huang, T.S.[Thomas S.], Torrellas, J.[Josep], Kang, Y.[Yi],
An IRAM Architecture for Image Analysis and Pattern Recognition,
ICPR98(Vol II: 1561-1564).
IEEE DOI 9808
BibRef

Kang, Y., Torrellas, J., Huang, T.S.,
Use IRAM for rasterization,
ICIP98(III: 1010-1013).
IEEE DOI 9810
BibRef

Zhang, B.[Bin], Lin, X.G.[Xing-Gang], Liao, Q.M.[Qing-Min],
An Object-Oriented System Architecture for General Image Processing Systems,
ICIP97(II: 688-691).
IEEE DOI 9710
BibRef

Ramamurti, V., Ghosh, J.,
Structural Adaptation in Mixture of Experts,
ICPR96(IV: 704-708).
IEEE DOI 9608
(Univ. of Texas, Austin, USA) BibRef

Noelle, M., Schreiber, G.,
Data Distribution Concepts for Parallel Image Processing,
ICPR96(IV: 728-733).
IEEE DOI 9608
(Technical Univ. Hamburg, D) BibRef

Parodi, G., Barbieri, I., Raggio, M.,
ACTS Project-AC077. Scalable architectures with hardware extensions for low bitrate variable bandwidth realtime videocommunications (SCALAR),
CIAP99(1206-1207).
IEEE DOI 9909
BibRef

di Gesù, V., Gerardi, G., Impedovo, S., Lenzitti, B., Parodi, G., Tegolo, D.,
A new heterogeneous and reconfigurable architecture for image analysis,
CAIP93(805-812).
Springer DOI 9309
BibRef

Jacobson, L., Wechsler, H.,
Invariant Architectures for Low-Level Vision,
CVIP92(141-166). BibRef 9200

Hsu, S.[Steve], Pearson, J.[John], Sajda, P.[Paul], and Spence, C.D.[Clay D.],
Neural Network/Pyramid Architectures That Learn Target Context,
ARPA94(II:853-862). BibRef 9400

Daida, J.M.,
Hybrid computational architectures for image segmentation,
ICIP94(III: 831-835).
IEEE DOI 9411
BibRef

Sajda, P., Spence, C.D., Pearson, J.,
A hierarchical neural network architecture that learns target context: applications to digital mammography,
ICIP95(III: 149-151).
IEEE DOI 9510
BibRef

Dunn, S.M.,
Writing retargetable parallel programs for low and high level vision using a global address space,
ICPR90(II: 591-595).
IEEE DOI 9208
BibRef

Olson, T.J., Bukys, L., Brown, C.M.,
Low Level Image Analysis on an MIMD Architecture,
ICCV87(468-475). BibRef 8700

Hogg, D.C.,
A Methodology for Real Time Scene Analysis,
IJCAI77(627). BibRef 7700

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Parallel and Multi-Processor Algorithms, General, Survey .


Last update:Sep 18, 2017 at 11:34:11